Abstract: The present disclosure provides an input device for an intelligent terminal, wherein the input device is in communication connection with the intelligent terminal and transmits a received input operation to the intelligent terminal, the input operation is displayed on a screen of the intelligent terminal, and the input device includes at least one operating portion; one end of the input device is recessed inwardly to form a recess, and the recess accommodates a top portion or a bottom portion of the intelligent terminal; when the input device is connected with the intelligent terminal, the top portion or the bottom portion of the intelligent terminal is inserted into the recess, the operating portion and the screen of the intelligent terminal are arranged on a same side, and a display interface of the screen of the intelligent terminal is exposed in a projection range of the operating portion.

Abstract: The present disclosure provides an input device for an intelligent terminal, a shell and an intelligent terminal, wherein the input device is in communication connection with the intelligent terminal, and the input device includes at least one operating portion and at least one first fixing portion; the input device is assembled and matched with the intelligent terminal through the shell, and an inside surface of the shell surrounds the intelligent terminal; an outside surface in a vertical direction of the shell is provided with a second fixing portion assembled and matched with the first fixing portion; when the first fixing portion and the second fixing portion are in an assembled state, the input device is located on one side of the shell in a horizontal direction; and when the shell is assembled with the intelligent terminal, an inside surface in a vertical direction corresponding to the second fixing portion is contacted with a top end surface or a bottom end surface of the intelligent terminal.

Abstract: A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.

Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.

Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

Abstract: A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.

Abstract: Disclosed herein are integrated circuit (IC) die stacks, as well as related apparatuses and methods. For example, in some embodiments, an IC package may include: a package substrate having a substrate conductive contact; a first die coupled to the package substrate, wherein the first die has a first face and an opposing second face, the second face of the first die is between the first face of the first die and the package substrate, and the first die has a first conductive contact at the first face of the first die; a second die coupled to the first die, wherein the second die has a second conductive contact facing the first face of the first die; and a bondwire between the first conductive contact and the substrate conductive contact, wherein the bondwire is also in electrical contact with the second conductive contact.

Abstract: Techniques for providing an integrated circuit package that avoids or eliminates x-y area and z-height compared to conventional integrated circuit packages. In certain examples, an example package can utilize a substrate with an opening and bottom side or sidewall terminations to avoid adding addition x-y substrate area or z-axis package height associated with an integrated circuit die of a stack of integrated circuit dies of the package.

Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

Abstract: A system in package includes a memory-die stack in memory module that is stacked vertically with respect to a processor die. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. Some configurations include the vertical bond wire emerging orthogonally beginning from a bond-wire pad. The matrix encloses the memory-die stack, the spacer, and at least a portion of the processor die.

Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and and at least a portion of the processor die. The matrix might also enclose the at least one additional component.

Abstract: A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.

Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution Layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

Abstract: A system in package and method for making a system in package. A plurality of passive devices are coupled to an interposer. A molding compound envelopes the plurality of passive devices and defines a platform having a substantially planar surface. The interposer is coupled to a substrate. A plurality of integrated circuit dies are coupled in a stack to the planar surface.