Abstract: The method includes: obtaining, in response to a write request for a target data block, a value of a first sub-counter corresponding to the target data block in an integrity tree, where the first sub-counter is a sub-counter of a first shared counter, and a first storage resource of the first sub-counter belongs to a storage resource of the first shared counter; and allocating a second storage resource to the first sub-counter when it is detected that a value obtained after a first value is added to the value of the first sub-counter is greater than a maximum storage value of the first storage resource. In this way, the adjusted storage resource of the first sub-counter is increased, thereby further preventing overflow of the first sub-counter and improving performance of data integrity verification of the integrity tree.

Abstract: This invention is related to an Express Traversal (EXTRA) Network on Chip (NoC) comprising a number of EXTRA routers. The EXTRA NoC comprises a Buffer Write and Route Computation (BW/RC) pipeline, a Switch Allocation-Local (SA-L) pipeline, a Setup Request (SR) pipeline, a Switch Allocation-Global (SA-G) pipeline, and a Switch Traversal and Link Traversal (ST/LT) pipeline. The BW/RC pipeline is configured to write an incoming flit to an input buffer(s) of a start EXTRA router and compute the route for the incoming head flit by selecting an output port to depart from the start EXTRA router. The SA-L pipeline is configured to arbitrate the start EXTRA router to choose an input port and an output port for a winning flit. The SR pipeline is configured to handle the transmission of a number of SR signals from the start EXTRA router to downstream EXTRA routers.

Abstract: A data processing method includes allocating a tag entry in a tag array for a data block; allocating a data entry in a data array for the data block when the data block is actively shared; and de-allocating the data entry when the data block is temporarily private or gets evicted in the data array.

Abstract: A data reader may have a magnetoresistive stack with a magnetically free layer decoupled from a first shield by a cap. The cap can have one or more sub-layers respectively configured with a thickness of 4 nm or less as measured parallel to a longitudinal axis of the magnetoresistive stack on an air bearing surface.

Abstract: Methods of planarizing materials, such as where surface topographies are created as part of a thin film device fabrication process are described. These methods find particular application in the creation of nano-sized devices, where surface topographical features can be effectively planarized without adversely creating other surface topographies and/or causing deleterious effects a material junctions. Methods include the step of depositing a sacrificial layer overlying at least a portion of a first material layer and at least a portion of a backfilled second material at a junction between the first and second materials. The sacrificial layer substantially retains the surface topography of the microelectronic device. Chemical-mechanical planarization is performed on a surface of the sacrificial layer but leaving a remainder portion of the thickness of the sacrificial layer.

Abstract: A magnetic stack is disclosed. The magnetic stack includes a magnetically responsive lamination that includes a ferromagnetic free layer, a synthetic antiferromagnetic (SAF) structure, and a spacer layer positioned between the ferromagnetic free layer and the SAF structure. The magnetically responsive lamination is separated from a sensed data bit stored in an adjacent medium by an air bearing surface (ABS). The stack also includes a first antiferromagnetic (AFM) structure coupled to the SAF structure a predetermined offset distance from the ABS, and a second AFM structure that is separated from the first AFM structure by a first shield layer.

Abstract: Embodiments of the application provide device, method and system for routing global assistant signals in a NoC. The device comprises: a signal distributing element having an associated intermediate router provided in a system for routing global assistant signals in a NoC which includes at least one intermediate router electrically interposed between a source router and a destination router, wherein the signal distributing element is configured to: based on a predetermined criterion, select either local global assistant signals generated by the associated intermediate router or upstream global assistant signals received from an upstream router of the associated intermediate router as current global assistant signals to be sent to a downstream router of the associated intermediate router.

Abstract: This invention is related to an Express Traversal (EXTRA) Network on Chip (NoC) comprising a number of EXTRA routers. The EXTRA NoC comprises a Buffer Write and Route Computation (BW/RC) pipeline, a Switch Allocation-Local (SA-L) pipeline, a Setup Request (SR) pipeline, a Switch Allocation-Global (SA-G) pipeline, and a Switch Traversal and Link Traversal (ST/LT) pipeline. The BW/RC pipeline is configured to write an incoming flit to an input buffer(s) of a start EXTRA router and compute the route for the incoming head flit by selecting an output port to depart from the start EXTRA router. The SA-L pipeline is configured to arbitrate the start EXTRA router to choose an input port and an output port for a winning flit. The SR pipeline is configured to handle the transmission of a number of SR signals from the start EXTRA router to downstream EXTRA routers.

Abstract: A data reader may have a magnetoresistive stack with a magnetically free layer decoupled from a first shield by a cap. The cap can have one or more sub-layers respectively configured with a thickness of 4 nm or less as measured parallel to a longitudinal axis of the magnetoresistive stack on an air bearing surface.

Abstract: Implementations described and claimed herein include a reader structure, comprising a first reader, including a sensor stack and a top shield structure, the top shield structure comprises a synthetic antiferromagnetic shield (SAF) structure, including a reference layer including at least a layer of NiFe and an impurity additive, an RKKY coupling layer RKKY coupling layer (e.g., Ru layer), and a pinned layer. In another implementation, the RL of the SAF shield structure of a first reader includes at least a layer of amorphous magnetic material. Yet, in another implementation, the SAF shield structure includes an insertion layer of amorphous magnetic material under the SAF shield RL, within the SAF shield RL or between the SAF shield RL and SAF shield Ru.

Abstract: A reconfigurable cache architecture is provided. In processor design, as the density of on-chip components increases, a quantity and complexity of processing cores will increase as well. In order to take advantage of increased processing capabilities, many applications will take advantage of instruction level parallelism. The reconfigurable cache architecture provides a cache memory that in capable of being configured in a private mode and a fused mode for an associated multi-core processor. In the fused mode, individual cores of the multi-core processor can write and read data from certain cache banks of the cache memory with greater control over address routing. The cache architecture further includes control and configurability of the memory size and associativity of the cache memory itself.

Abstract: The embodiment of the disclosure discloses a data processing method and device in a cache coherence directory architecture. The method includes that allocating a tag entry in a tag array for a data block; allocating a data entry in a data array for the data block when the data block is actively shared; and de-allocating the data entry when the data block is temporarily private or gets evicted in the data array. Therefore the embodiments of the disclosure allocate data entry only when a data block is actively shared and will not allocate data entry for data block which is not actively shared, therefore smaller directory size can be achieved.

Abstract: Implementations described and claimed herein include a reader structure, comprising a first reader, including a sensor stack and a top shield structure, the top shield structure comprises a synthetic antiferromagnetic shield (SAF) structure, including a reference layer including at least a layer of NiFe and an impurity additive, an RKKY coupling layer RKKY coupling layer (e.g., Ru layer), and a pinned layer. In another implementation, the RL of the SAF shield structure of a first reader includes at least a layer of amorphous magnetic material. Yet, in another implementation, the SAF shield structure includes an insertion layer of amorphous magnetic material under the SAF shield RL, within the SAF shield RL or between the SAF shield RL and SAF shield Ru.

Abstract: A data reader may have a magnetoresistive stack with a magnetically free layer decoupled from a first shield by a cap. The cap can have one or more sub-layers respectively configured with a thickness of 4 nm or less as measured parallel to a longitudinal axis of the magnetoresistive stack on an air bearing surface.

Abstract: A multi-sensor reader that includes a first sensor that has a sensing layer with a magnetization that changes according to an external magnetic field. The first sensor also includes first and second side biasing magnets having a magnetization substantially along a first direction. The first and second side biasing magnets align the magnetization of the sensing layer substantially along the first direction when the sensing layer is not substantially influenced by the external magnetic field. The multi-sensor reader further includes a second sensor that is stacked over the first sensor. The second sensor includes a reference layer that has a magnetization that is set substantially along a second direction.

Abstract: A reader stack, such as for a magnetic storage device, the stack having a top synthetic antiferromagnetic (SAF) layer, a magnetic capping layer adjacent to the top SAF layer, an RKKY coupling layer adjacent to the magnetic capping layer opposite the top SAF layer, and a free layer adjacent to the RKKY coupling layer opposite the magnetic capping layer. Also included is a method for biasing a free layer in a reader stack by providing an exchange coupling between the free layer and a top synthetic antiferromagnetic (SAF) layer using a layer having RKKY coupling property positioned between the free layer and the top SAF layer and a magnetic capping layer between the SAF layer and the layer having RKKY coupling property.

Abstract: A multi-sensor reader that includes a first sensor that has a sensing layer with a magnetization that changes according to an external magnetic field. The first sensor also includes first and second side biasing magnets having a magnetization substantially along a first direction. The first and second side biasing magnets align the magnetization of the sensing layer substantially along the first direction when the sensing layer is not substantially influenced by the external magnetic field. The multi-sensor reader further includes a second sensor that is stacked over the first sensor. The second sensor includes a reference layer that has a magnetization that is set substantially along a second direction.

Abstract: A multi-sensor reader that includes a first sensor that has a sensor stack, which includes a free layer (FL) that has a magnetization that changes according to an external magnetic field. The first sensor also includes a shielding structure that is positioned over the sensor stack. The multi-sensor reader also includes a second sensor stacked over the first sensor. The second sensor includes a sensor stack, which includes a FL that has a magnetization that changes according to the external magnetic field. The multi-sensor reader further includes an isolation layer between the first sensor and the second sensor. A FL-to-FL spacing reduction feature is included in at least one of the isolation layer or the shielding structure.

Abstract: Implementations described and claimed herein include a reader structure, comprising a first reader, including a sensor stack and a top shield structure, the top shield structure comprises a synthetic antiferromagnetic shield (SAF) structure, including a reference layer including at least a layer of NiFe and an impurity additive, an RKKY coupling layer RKKY coupling layer (e.g., Ru layer), and a pinned layer. In another implementation, the RL of the SAF shield structure of a first reader includes at least a layer of amorphous magnetic material. Yet, in another implementation, the SAF shield structure includes an insertion layer of amorphous magnetic material under the SAF shield RL, within the SAF shield RL or between the SAF shield RL and SAF shield Ru.

Abstract: A reconfigurable cache architecture is provided. In processor design, as the density of on-chip components increases, a quantity and complexity of processing cores will increase as well. In order to take advantage of increased processing capabilities, many applications will take advantage of instruction level parallelism. The reconfigurable cache architecture provides a cache memory that in capable of being configured in a private mode and a fused mode for an associated multi-core processor. In the fused mode, individual cores of the multi-core processor can write and read data from certain cache banks of the cache memory with greater control over address routing. The cache architecture further includes control and configurability of the memory size and associativity of the cache memory itself.