Abstract: A reconfigurable cache architecture is provided. In processor design, as the density of on-chip components increases, a quantity and complexity of processing cores will increase as well. In order to take advantage of increased processing capabilities, many applications will take advantage of instruction level parallelism. The reconfigurable cache architecture provides a cache memory that in capable of being configured in a private mode and a fused mode for an associated multi-core processor. In the fused mode, individual cores of the multi-core processor can write and read data from certain cache banks of the cache memory with greater control over address routing. The cache architecture further includes control and configurability of the memory size and associativity of the cache memory itself.

Abstract: A magnetic stack is disclosed. The magnetic stack includes a magnetically responsive lamination that includes a ferromagnetic free layer, a synthetic antiferromagnetic (SAF) structure, and a spacer layer positioned between the ferromagnetic free layer and the SAF structure. The magnetically responsive lamination is separated from a sensed data bit stored in an adjacent medium by an air bearing surface (ABS). The stack also includes a first antiferromagnetic (AFM) structure coupled to the SAF structure a predetermined offset distance from the ABS, and a second AFM structure that is separated from the first AFM structure by a first shield layer.

Abstract: The implementations disclosed herein provide for a spin transport sensor including a synthetic antiferromagnet (SAF) adjacent a shield element. The SAF extends to an air-bearing surface (ABS) and provides a current path from a current source to an ABS-region of a spin conductor layer. Spin current diffuses from the spin conductor layer to an adjacent free layer, which generates a measurable electrical voltage in a free layer of the spin transport sensor. The SAF serves as both a magnetic shield and a spin injector to the spin conductor layer.

Abstract: A magnetic stack is disclosed. The magnetic stack includes a magnetically responsive lamination that includes a ferromagnetic free layer, a synthetic antiferromagnetic (SAF) structure, and a spacer layer positioned between the ferromagnetic free layer and the SAF structure. The magnetically responsive lamination is separated from a sensed data bit stored in an adjacent medium by an air bearing surface (ABS). The stack also includes a first antiferromagnetic (AFM) structure coupled to the SAF structure a predetermined offset distance from the ABS, and a second AFM structure that is separated from the first AFM structure by a first shield layer.

Abstract: A reader stack, such as for a magnetic storage device, the stack having a top synthetic antiferromagnetic (SAF) layer, a magnetic capping layer adjacent to the top SAF layer, an RKKY coupling layer adjacent to the magnetic capping layer opposite the top SAF layer, and a free layer adjacent to the RKKY coupling layer opposite the magnetic capping layer. Also included is a method for biasing a free layer in a reader stack by providing an exchange coupling between the free layer and a top synthetic antiferromagnetic (SAF) layer using a layer having RKKY coupling property positioned between the free layer and the top SAF layer and a magnetic capping layer between the SAF layer and the layer having RKKY coupling property.

Abstract: The implementations disclosed herein provide for a spin transport sensor including a synthetic antiferromagnet (SAF) adjacent a shield element. The SAF extends to an air-bearing surface (ABS) and provides a current path from a current source to an ABS-region of a spin conductor layer. Spin current diffuses from the spin conductor layer to an adjacent free layer, which generates a measurable electrical voltage in a free layer of the spin transport sensor. The SAF serves as both a magnetic shield and a spin injector to the spin conductor layer.

Abstract: A reconfigurable cache architecture is provided. In processor design, as the density of on-chip components increases, a quantity and complexity of processing cores will increase as well. In order to take advantage of increased processing capabilities, many applications will take advantage of instruction level parallelism. The reconfigurable cache architecture provides a cache memory that in capable of being configured in a private mode and a fused mode for an associated multi-core processor. In the fused mode, individual cores of the multi-core processor can write and read data from certain cache banks of the cache memory with greater control over address routing. The cache architecture further includes control and configurability of the memory size and associativity of the cache memory itself.

Abstract: The implementations disclosed herein provide for a spin transport sensor including a synthetic antiferromagnet (SAF) adjacent a shield element. The SAF extends to an air-bearing surface (ABS) and provides a current path from a current source to an ABS-region of a spin conductor layer. Spin current diffuses from the spin conductor layer to an adjacent free layer, which generates a measurable electrical voltage in a free layer of the spin transport sensor. The SAF serves as both a magnetic shield and a spin injector to the spin conductor layer.

Abstract: The implementations disclosed herein provide for a spin transport sensor including a synthetic antiferromagnet (SAF) adjacent a shield element. The SAF extends to an air-bearing surface (ABS) and provides a current path from a current source to an ABS-region of a spin conductor layer. Spin current diffuses from the spin conductor layer to an adjacent free layer, which generates a measurable electrical voltage in a free layer of the spin transport sensor. The SAF serves as both a magnetic shield and a spin injector to the spin conductor layer.

Abstract: A magnetic element is generally provided that can be implemented as a data reader. Various embodiments may connect a magnetic stack to a top shield and separate the magnetic stack from a bi-layer side shield. The bi-layer side shield may have a fixed magnetization layer and a soft magnetic layer each magnetically isolated from the top shield.

Abstract: A magnetic element is generally provided that can be implemented as a data reader. Various embodiments may connect a magnetic stack to a top shield and separate the magnetic stack from a bi-layer side shield. The bi-layer side shield may have a fixed magnetization layer and a soft magnetic layer each magnetically isolated from the top shield.