Abstract: Embodiments of a microelectronic assembly that includes: a package substrate, comprising buildup layers of an organic dielectric material and a plurality of layers of conductive traces in the organic dielectric material, the package substrate having a first surface and a second surface opposite the first surface; and a plurality of integrated circuit (IC) dies coupled to the package substrate on the first side. The plurality of layers of conductive traces comprises a pair of stripline traces or microstrips in one of the layers, the stripline traces or microstrips are surrounded by air gap structures in the organic dielectric material, and the air gap structures are exposed on the first surface.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Abstract: Methods, systems, apparatus, and articles of manufacture to produce integrated circuit packages with grounding members are disclosed. An example semiconductor die disclosed herein includes a semiconductor substrate, metal interconnects proximate a first side of the semiconductor substrate, a metal contact proximate a second side of the semiconductor substrate opposite the first side, a first grounding member extending from a grounding interconnect of the metal interconnects to a first distal point in the semiconductor substrate, and a second grounding member extending from the metal contact to a second distal point in the semiconductor substrate, the first distal point closer to the first side of the semiconductor substrate than the second distal point is to the first side of the semiconductor substrate.

Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Abstract: An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

Abstract: An electronic device includes a substrate including a core layer having a first surface and a second surface opposite the first surface, and at least one coaxial through-hole extending vertically through the core layer from the first surface to the second surface. The coaxial through-hole includes at least a first through-via that includes electrically conductive material extending through the core layer from the first surface to the second surface, and a conductive layer including the same or different electrically conductive material extending vertically through the core layer from the first surface to the second surface and surrounding the first through-via. The conductive layer is to be connected to a ground voltage and is electrically isolated from the first through-via.

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate having a first face and an opposing second face, the package substrate comprising a conductive trace in a dielectric material, a conductive structure at least partially surrounding the conductive trace and separated from the conductive trace by the dielectric material; and an integrated circuit (IC) die attached to the first face of the package substrate and coupled to the conductive trace by a conductive pathway through the package substrate. The conductive trace has a non-rectangular cross-section with rounded corners, the conductive structure comprises a plurality of conductive planes parallel to the conductive trace and coupled to a ground connection.

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate comprising a conductive trace in a dielectric material, the conductive trace surrounded by a conductive structure coupled to a ground connection, the package substrate further comprising metallization layers alternating with dielectric layers of the dielectric material; and an integrated circuit (IC) die coupled to a surface of the package substrate, the IC die being coupled to the conductive trace by a conductive pathway. The dielectric layers and the metallization layers are parallel to the surface of the package substrate, the conductive trace comprises a trench via in one of the dielectric layers, and the conductive structure comprises grounded plates extending across a length and width of the package substrate in metallization layers on either side of the dielectric layer.

Abstract: Disclosed herein are silver-coated conductive structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a first material layer on a top surface and on side surfaces of the conductive line, the first material layer including silver, and a second material layer on the first material layer, the second material layer including silicon or aluminum, and one or more of nitrogen and oxygen.

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

Abstract: Embodiments disclosed herein include electronic packages In an embodiment, the electronic package comprises first substrate layers, and a core under the first substrate layers. In an embodiment, second substrate layers are under the core, and an interconnect is through the first substrate layers, the core, and the second substrate layers. In an embodiment, a portion of the interconnect through the second substrate layers comprises a pad, and a plurality of vias extending away from the pad.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

Abstract: A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; physical layer (PHY) circuitry on the substrate including a plurality of receive (RX) circuits and a plurality of transmit (TX) circuits; electrical contact structures at a bottom surface of the device; signal routing paths extending between the electrical contact structures on one hand, and, on another hand, at least some of the RX circuits or at least some of the TX circuits; and electrical pathways leading to the PHY circuitry and configured such that at least one of: an enable signal input to the device is to travel through at least some of the electrical pathways to enable a portion of the PHY circuitry; or a disable signal input to the device is to travel through at least some of the electrical pathways to disable a corresponding portion of the PHY circuitry.

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.