Patents by Inventor Zhiguo Qian

Zhiguo Qian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210327795
    Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.
    Type: Application
    Filed: June 28, 2021
    Publication date: October 21, 2021
    Applicant: Intel Corporation
    Inventors: Zhiguo QIAN, Kaladhar RADHAKRISHNAN, Kemal AYGUN
  • Publication number: 20210296242
    Abstract: A device and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Inventors: MD Altaf Hossain, Kevin J. Doran, Yu Amos Zhang, Zhiguo Qian
  • Patent number: 11094633
    Abstract: A microelectronic package bridge can comprising a plurality of ground layers, and a plurality of signal layers interwoven with the plurality of ground layers. Each of the signal layers can include a plurality of electrically conductive pathways. Each of the electrically conductive pathways can be arranged to form an electrical connection between one of a first plurality of bumps of a first die and one of a second plurality of bumps of a second die. Each of the plurality of electrically conductive pathways can have a length substantially equal to one another.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kemal Aygun, Dae-Woo Kim, Jackie C. Preciado
  • Patent number: 11081434
    Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kaladhar Radhakrishnan, Kemal Aygun
  • Patent number: 11031341
    Abstract: A device and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Md Altai Hossain, Kevin J Doran, Yu Amos Zhang, Zhiguo Qian
  • Publication number: 20210167015
    Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 3, 2021
    Inventors: Zhiguo Qian, Kemal Aygun
  • Publication number: 20210125912
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first buildup layer and a second buildup layer over the first buildup layer. In an embodiment, a void is disposed through the second buildup layer. In an embodiment the electronic package further comprises a first pad over the second buildup layer. In an embodiment, the first pad covers the void.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Inventors: Zhiguo QIAN, Gang DUAN, Kemal AYGÜN, Jieying KONG, Brandon C. MARIN
  • Publication number: 20210104476
    Abstract: Embodiments include package substrates and a semiconductor package with such package substrates. A package substrate includes a first conductive layer in a first magnetic layer, and a second magnetic layer over the first magnetic layer, where the first and second magnetic layers include magnetic materials. The package substrate also includes a second conductive layer in the second magnetic layer. The second conductive layer includes a plurality of first traces fully surrounded by the first and second magnetic layers. The package substrate includes a third conductive layer over the second magnetic layer. The magnetic materials may include manganese Mn ferrite materials, Zn/Mn ferrite materials, or Ni/Zn ferrite materials. The magnetic materials include material properties with a low constant value, a magnetic tangent value, a frequency, a base filler chemistry, a filler shape, a filler orientation, a filler percentage, a loading fraction value, a permeability, an insertion loss, and a resin formulation.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 8, 2021
    Inventors: Zhiguo QIAN, Cemil GEYIK, Jiwei SUN, Gang DUAN, Kemal AYGÜN
  • Patent number: 10950550
    Abstract: Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Jianyong Xie, Kemal Aygun
  • Publication number: 20210057321
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 25, 2021
    Inventors: Zhiguo Qian, Kemal Aygun, Yu Zhang
  • Publication number: 20210057345
    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.
    Type: Application
    Filed: November 6, 2020
    Publication date: February 25, 2021
    Inventors: Henning Braunisch, Kemal Aygun, Ajay Jain, Zhiguo Qian
  • Patent number: 10892225
    Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kemal Aygun
  • Patent number: 10867926
    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Kemal Aygun, Ajay Jain, Zhiguo Qian
  • Publication number: 20200388572
    Abstract: An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 30, 2018
    Publication date: December 10, 2020
    Applicant: INTEL CORPORATION
    Inventors: Kemal Aygun, Zhiguo Qian, Jianyong Xie
  • Publication number: 20200381350
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 3, 2020
    Inventors: Sujit SHARAN, Kemal AYGUN, Zhiguo QIAN, Yidnekachew MEKONNEN, Zhichao ZHANG, Jianyong XIE
  • Patent number: 10854539
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kemal Aygun, Yu Zhang
  • Publication number: 20200373232
    Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Applicant: Intel Corporation
    Inventors: Zhiguo QIAN, Kaladhar RADHAKRISHNAN, Kemal AYGUN
  • Patent number: 10845552
    Abstract: An optoelectronic apparatus is presented. In embodiments, the apparatus may include a package including a substrate with a first side and a second side opposite the first side, wherein the first side comprises a ball grid array (BGA) field. The apparatus may further include one or more integrated circuits (ICs) disposed on the first side of the substrate, inside the BGA field, that thermally interface with a printed circuit board (PCB), to which the package is to be coupled, one or more optical ICs coupled to the second side and communicatively coupled with the one or more ICs via interconnects provided in the substrate, wherein at least one of the optical ICs is at least partially covered by an integrated heat spreader (IHS), to provide dissipation of heat produced by the at least one optical IC.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Henning Braunisch, Timothy A. Gosselin, Prasanna Raghavan, Yikang Deng, Zhiguo Qian
  • Patent number: 10840196
    Abstract: Disclosed embodiments include a signal trace in an integrated-circuit device package substrate. Portions of the signal traces, suspend a landing pad in a recess, and a portion of the suspended signal trace is form-factor modulated that is different in cross-section area than other portions of the suspended signal trace.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Cemil Geyik, Zhiguo Qian
  • Patent number: 10833020
    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: November 10, 2020
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Kemal Aygun, Ajay Jain, Zhiguo Qian