Abstract: Embodiments include electronic packages and methods of forming such packages. An electronic package includes a memory module comprising a first memory die. The first memory die includes first interconnects with a first pad pitch and second interconnects with a second pad pitch, where the second pad pitch is less than the first pad pitch. The memory module also includes a redistribution layer below the first memory die, and a second memory die below the redistribution layer, where the second memory die has first interconnects with a first pad pitch and second interconnects with a second pad pitch. The memory module further includes a mold encapsulating the second memory die, where through mold interconnects (TMIs) provide an electrical connection from the redistribution layer to mold layer. The TMIs may be through mold vias. The TMIs may be made through a passive interposer that is encapsulated in the mold.

Abstract: A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a first surface and an opposing second surface, wherein the first die is in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, wherein the magnetic core inductor may include a first conductive pillar at least partially surrounded by a magnetic material, and a second conductive pillar coupled to the first conductive pillar; and a second die having a first surface and an opposing second surface, wherein the second die is in a second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the magnetic core inductor.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate; a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; and a shield structure that at least partially surrounds the conductive pillar.

Abstract: A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical, isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance.

Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.

Abstract: A device and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Abstract: An optoelectronic apparatus is presented. In embodiments, the apparatus may include a package including a substrate with a first side and a second side opposite the first side, wherein the first side comprises a ball grid array (BGA) field. The apparatus may further include one or more integrated circuits (ICs) disposed on the first side of the substrate, inside the BGA field, that thermally interface with a printed circuit board (PCB), to which the package is to be coupled, one or more optical ICs coupled to the second side and communicatively coupled with the one or more ICs via interconnects provided in the substrate, wherein at least one of the optical ICs is at least partially covered by an integrated heat spreader (IHS), to provide dissipation of heat produced by the at least one optical IC.

Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.

Abstract: Apparatuses, systems and methods associated with integrated circuit packages with integrated test circuitry for testing of a channel between dies are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first die, a second die, and a channel that couples the first die to the second die. The first die may include a transmitter, test circuitry coupled between the transmitter and the channel, wherein the test circuitry is to control charge and discharge of the channel, and a receiver coupled to the channel. The receiver may determine a voltage of the channel during charge and discharge of the channel, and output an indication of the voltage. Other embodiments may be described and/or claimed.

Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia).

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

Abstract: A microelectronic package bridge can comprising a plurality of ground layers, and a plurality of signal layers interwoven with the plurality of ground layers. Each of the signal layers can include a plurality of electrically conductive pathways. Each of the electrically conductive pathways can be arranged to form an electrical connection between one of a first plurality of bumps of a first die and one of a second plurality of bumps of a second die. Each of the plurality of electrically conductive pathways can have a length substantially equal to one another.

Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.

Abstract: One embodiment provides an apparatus. The apparatus includes a dual in-line memory module (DIMM). The DIMM includes at least one memory module integrated circuit (IC); a DIMM printed circuit board (PCB); a plurality of DIMM PCB contacts; and a capacitive structure. Each DIMM PCB contact is to couple the memory module IC to a respective DIMM connector pin. The capacitive structure is to provide a mutual capacitance between a first DIMM connector signal pin and a second DIMM connector signal pin.

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.