Abstract: An electronic device may be provided with a display. The display may be overlapped by an antiglare film. The antiglare film may have a rough surface to diffuse incident light, thereby reducing glare. Additionally, the antiglare film may have a smooth portion that forms a transparent window and allows light to pass through undiffused. The electronic device may include a light-based component, such as a camera, that receives undiffused light through the transparent window. By overlapping the light-based component with the transparent window, the light-based component may receive the light in an unimpeded manner, thereby making more accurate measurements of the light. The display may have one or more display layers, such as opaque masking layers or polarizers, with openings that are aligned with the transparent window. The light-based component may receive the light through these openings so that the light is not absorbed or polarized before reaching the component.

Abstract: Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display apparatus. The array substrate includes a plurality of pad structures located in a bonding region and a plurality of data leads located in a lead region. Each data lead corresponds to one pad structure. The pad structure includes at least two pad electrodes insulated from each other. In the pad structure, each pad electrode is electrically connected to the data lead corresponding to the pad structure, respectively, to form different signal writing paths.

Abstract: The present disclosure provides a mask plate, a method for forming a via-hole, a method for forming a display substrate, the display substrate, and a display device. The mask plate is configured to form the via-hole in a layer, and includes a transparent pattern for the formation of the via-hole. The transparent pattern includes one or more curved edge, so the via-hole formed using the mask plate is provided with one or more curved edges at its bottom.

Abstract: Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display apparatus. The array substrate includes a plurality of pad structures located in a bonding region and a plurality of data leads located in a lead region. Each data lead corresponds to one pad structure. The pad structure includes at least two pad electrodes insulated from each other. In the pad structure, each pad electrode is electrically connected to the data lead corresponding to the pad structure, respectively, to form different signal writing paths.

Abstract: Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display apparatus. The array substrate includes a plurality of pad structures located in a bonding region and a plurality of data leads located in a lead region. Each data lead corresponds to one pad structure. The pad structure includes at least two pad electrodes insulated from each other. In the pad structure, each pad electrode is electrically connected to the data lead corresponding to the pad structure, respectively, to form different signal writing paths.

Abstract: The present disclosure provides a mask plate, a method for forming a via-hole, a method for forming a display substrate, the display substrate, and a display device. The mask plate is configured to form the via-hole in a layer, and includes a transparent pattern for the formation of the via-hole. The transparent pattern includes one or more curved edge, so the via-hole formed using the mask plate is provided with one or more curved edges at its bottom.

Abstract: The present disclosure provides a fan-out structure and a method for manufacturing the same, and a display panel, relating to the field of display technology. The fan-out structure includes a plurality of fan-out units for connecting a drive circuit to a display area, wherein each of the fan-out units includes a fan-out line, and at least one of the fan-out units further includes a resistance adjustment unit connected to a corresponding fan-out line, and the resistance adjustment unit is configured to make a resistance difference between different fan-out units smaller than a first threshold.

Abstract: The present disclosure provides a pixel structure, a display panel and a fabrication method thereof, and a display device. The pixel structure includes a substrate and an inorganic photoluminescent layer formed on the substrate. The pixel structure incudes an excitation layer disposed on a side of the inorganic photoluminescent layer away from the substrate and configured to excite the inorganic photoluminescent layer to emit light. The pixel structure includes an organic light-emitting layer in the same layer as the excitation layer. A space is disposed between the organic light-emitting layer and the excitation layer. An orthographic projection of the excitation layer on the substrate overlaps at least partially an orthographic projection of the inorganic photoluminescent layer on the substrate.

Abstract: The present disclosure relates to the field of display technology, in particular to a display panel, a manufacturing method thereof, and a display device. The display panel includes a display substrate and an encapsulation layer for encapsulating the display substrate. The encapsulation layer includes at least one inorganic composite film layer, and each inorganic composite film layer includes an inorganic matrix and an inorganic filler. The inorganic matrix includes a plurality of grains spaced apart by gaps, and the inorganic filler is capable of enclosing each grain and being filled in a gap between every two adjacent grains.

Abstract: The present disclosure provides a fan-out structure and a method for manufacturing the same, and a display panel, relating to the field of display technology. The fan-out structure includes a plurality of fan-out units for connecting a drive circuit to a display area, wherein each of the fan-out units includes a fan-out line, and at least one of the fan-out units further includes a resistance adjustment unit connected to a corresponding fan-out line, and the resistance adjustment unit is configured to make a resistance difference between different fan-out units smaller than a first threshold.

Abstract: An array substrate, a method for manufacturing the same, a liquid crystal display panel, and a display device are provided. The array substrate includes a first substrate, signal lines and an insulating layer; the insulating layer is disposed on the first substrate, and grooves are disposed on a side of the insulating layer facing away from the first substrate and disposed in a region of the insulating layer corresponding to a non-display region of the array substrate; and the signal lines are disposed on inner walls of the grooves, a direction of the inner walls of the grooves is arranged such that at least a portion of light incident on the signal lines from a side of the first substrate facing away from the signal lines is reflected to a display region of the array substrate.

Abstract: An array substrate, a method for manufacturing the same, a liquid crystal display panel, and a display device are provided. The array substrate includes a first substrate; signal lines and an insulating layer; the insulating layer is disposed on the first substrate, and grooves are disposed on a side of the insulating layer facing away from the first substrate and disposed in a region of the insulating layer corresponding to a non-display region of the arm substrate; and the signal lines are disposed on inner walls of the grooves, a direction of the inner walls of the grooves is arranged such that at least a portion of light incident on the signal lines from a side of the first substrate facing away from the signal lines is reflected to a display region of the array substrate.

Abstract: A pixel structure, a display panel and a display device are provided. The pixel structure includes: a base substrate; a plurality of gate lines; a plurality of data lines; a plurality of pixel units, each includes a pixel electrode and a common electrode; and a common electrode line connected with the common electrode, wherein, the common electrode line includes a first part extended along the row direction and a second part extended along the column direction; the first part is electrically connected with the second part; both the first part and the second part are arranged in a same layer with the plurality of data lines; and a projection of the first part on the base substrate is at least partially disposed between projections of a gate line among the plurality of gate lines which is closest to the first part and the pixel electrode on the base substrate.

Abstract: The present disclosure provides a pixel structure, a display panel and a fabrication method thereof, and a display device. The pixel structure includes a substrate and an inorganic photoluminescent layer formed on the substrate. The pixel structure incudes an excitation layer disposed on a side of the inorganic photoluminescent layer away from the substrate and configured to excite the inorganic photoluminescent layer to emit light. The pixel structure includes an organic light-emitting layer in the same layer as the excitation layer. A space is disposed between the organic light-emitting layer and the excitation layer. An orthographic projection of the excitation layer on the substrate overlaps at least partially an orthographic projection of the inorganic photoluminescent layer on the substrate.

Abstract: Disclosure are an array substrate, a display panel and a display device. The array substrate includes a base substrate and a plurality of pixel units disposed on the base substrate. Each of the pixel units includes a first subpixel unit and a second subpixel unit; the first subpixel unit includes a first pixel electrode and a first common electrode; the second subpixel unit includes a second pixel electrode and a second common electrode which are insulated from each other; the first pixel electrode is electrically connected with the second pixel electrode; and the stacking sequence of the first pixel electrodes and the first common electrodes in the direction perpendicular to the base substrate is opposite to the stacking sequence of the second pixel electrodes and the second common electrodes in the direction perpendicular to the base substrate. The array substrate can effectively improve poor quality such as afterimage.

Abstract: A TFT array substrate, its manufacturing method and a corresponding display device are disclosed. The TFT array substrate, includes a bearing substrate, a gate line and a data line arranged across each other on the bearing substrate, a pixel region defined by the gate line and the data line, and a thin film transistor, a pixel electrode and an active layer disposed in the pixel region. Specifically, a gate of the thin film transistor is connected to the gate line, a source thereof is connected to the data line and a drain thereof is connected to the pixel electrode. Further, an insulating layer is also formed above the source of the thin film transistor, and a drain trench is formed in the insulating layer. In addition, the drain of the thin film transistor is in the drain trench and is connected to the source through the active layer.

Abstract: A thin film transistor comprises a gate, a gate insulating layer, an active layer, a source electrode and a drain electrode. The drain electrode comprises a first sub-drain electrode and at least one second sub-drain electrode. A first portion of the active layer between the first sub-drain electrode and the source electrode and a second portion of the active layer between each of the at least one second sub-drain electrode and the source electrode are used for forming different portions of a primary channel, respectively. The first sub-drain electrode is a signal input electrode, and a third portion of the active layer between the first sub-drain electrode and each of the at least one second sub-drain electrode is used for forming an auxiliary channel. A channel length of the auxiliary channel is less than or equal to a channel length of the primary channel.

Abstract: The present disclosure relates to the field of display technology, in particular to a display panel, a manufacturing method thereof, and a display device. The display panel includes a display substrate and an encapsulation layer for encapsulating the display substrate. The encapsulation layer includes at least one inorganic composite film layer, and each inorganic composite film layer includes an inorganic matrix and an inorganic filler. The inorganic matrix includes a plurality of grains spaced apart by gaps, and the inorganic filler is capable of enclosing each grain and being filled in a gap between every two adjacent grains.

Abstract: A TFT and a method for manufacturing the same, an array substrate and a display device are provided. The TFT includes a first electrode pattern and a second electrode pattern arranged at an identical layer. The first electrode pattern includes a first strip-like portion extending in a first direction, and the second electrode pattern includes a bending portion surrounding a first end of the first strip-like portion. The second electrode pattern further includes a second strip-like portion extending from a first end of the bending portion in the first direction. A channel formation region of the TFT includes a region between the bending portion and the first strip-like portion, and a region between the second strip-like portion and the first strip-like portion.

Abstract: It is provided a grayscale voltage debugging method for debugging a display device including a white subpixel, including a first step of, in a state where the white subpixel is disenabled and subpixels in other colors are enabled, adjusting a respective to-be-adjusted grayscale voltage applied to each of the subpixels in other colors, so that a first actually-measured Gamma curve corresponding to the respective adjusted grayscale voltage is located within an acceptable range of a standard Gamma curve, and a second step of, in a state where the white subpixel and the subpixels in other colors are all enabled, acquiring a second actually-measured Gamma curve and in the case that the second actually-measured Gamma curve is not located within the acceptable range, changing the respective adjusted grayscale voltage to obtain a new respective to-be-adjusted grayscale voltage, and returning to the first step.