Abstract: An array substrate, a method for forming an array substrate, a display panel and a display device are provided, which relate to the field of display technology. The array substrate includes a functional film layer pattern on a base substrate and an insulating layer covering the functional film layer pattern, and a segment difference of a surface of the insulating layer is smaller than a segment difference threshold.

Abstract: It is provided a grayscale voltage debugging method for debugging a display device including a white subpixel, including a first step of, in a state where the white subpixel is disenabled and subpixels in other colors are enabled, adjusting a respective to-be-adjusted grayscale voltage applied to each of the subpixels in other colors, so that a first actually-measured Gamma curve corresponding to the respective adjusted grayscale voltage is located within an acceptable range of a standard Gamma curve, and a second step of, in a state where the white subpixel and the subpixels in other colors are all enabled, acquiring a second actually-measured Gamma curve and in the case that the second actually-measured Gamma curve is not located within the acceptable range, changing the respective adjusted grayscale voltage to obtain a new respective to-be-adjusted grayscale voltage, and returning to the first step.

Abstract: The present application discloses a display panel having a plurality of gate lines and a gate driving circuit for driving the plurality of gate lines, the gate driving circuit including a plurality of first cascaded shift register units and a plurality of second cascaded shift register units for applying gate scanning signals to gate lines connected thereto.

Abstract: A thin film transistor comprises a gate, a gate insulating layer, an active layer, a source electrode and a drain electrode. The drain electrode comprises a first sub-drain electrode and at least one second sub-drain electrode. A first portion of the active layer between the first sub-drain electrode and the source electrode and a second portion of the active layer between each of the at least one second sub-drain electrode and the source electrode are used for forming different portions of a primary channel, respectively. The first sub-drain electrode is a signal input electrode, and a third portion of the active layer between the first sub-drain electrode and each of the at least one second sub-drain electrode is used for forming an auxiliary channel. A channel length of the auxiliary channel is less than or equal to a channel length of the primary channel.

Abstract: A TFT and a method for manufacturing the same, an array substrate and a display device are provided. The TFT includes a first electrode pattern and a second electrode pattern arranged at an identical layer. The first electrode pattern includes a first strip-like portion extending in a first direction, and the second electrode pattern includes a bending portion surrounding a first end of the first strip-like portion. The second electrode pattern further includes a second strip-like portion extending from a first end of the bending portion in the first direction. A channel formation region of the TFT includes a region between the bending portion and the first strip-like portion, and a region between the second strip-like portion and the first strip-like portion.

Abstract: A TFT array substrate, its manufacturing method and a corresponding display device are disclosed. The TFT array substrate, includes a bearing substrate, a gate line and a data line arranged across each other on the bearing substrate, a pixel region defined by the gate line and the data line, and a thin film transistor, a pixel electrode and an active layer disposed in the pixel region. Specifically, a gate of the thin film transistor is connected to the gate line, a source thereof is connected to the data line and a drain thereof is connected to the pixel electrode. Further, an insulating layer is also formed above the source of the thin film transistor, and a drain trench is formed in the insulating layer. In addition, the drain of the thin film transistor is in the drain trench and is connected to the source through the active layer.

Abstract: An array substrate, a method for forming an array substrate, a display panel and a display device are provided, which relate to the field of display technology. The array substrate includes a functional film layer pattern on a base substrate and an insulating layer covering the functional film layer pattern, and a segment difference of a surface of the insulating layer is smaller than a segment difference threshold.

Abstract: A pixel structure, a display panel and a display device are provided. The pixel structure includes: a base substrate; a plurality of gate lines; a plurality of data lines; a plurality of pixel units, each includes a pixel electrode and a common electrode; and a common electrode line connected with the common electrode, wherein, the common electrode line includes a first part extended along the row direction and a second part extended along the column direction; the first part is electrically connected with the second part; both the first part and the second part are arranged in a same layer with the date line; and a projection of the first part on the base substrate is at least partially disposed between projections of the gate line and the pixel electrode on the base substrate.

Abstract: The present application discloses a display panel having a plurality of gate lines and a gate driving circuit for driving the plurality of gate lines, the gate driving circuit including a plurality of first cascaded shift register units and a plurality of second cascaded shift register units for applying gate scanning signals to gate lines connected thereto.

Abstract: A signal adjusting circuit and a display panel driving circuit are disclosed. The signal adjusting circuit includes an input terminal, a control terminal, an output terminal, a selection module and a delay module. The selection module is configured to selectively transfer an input signal received via the input terminal to the output terminal depending on an indication signal received via the control terminal. The delay module is configured to delay the input signal received from the selection module by an amount of time and transfer the delayed input signal to the output terminal. The display panel driving circuit includes one or more signal adjusting circuits to adjust periodic output enable pulses that enable outputting of gate scan pulses.

Abstract: A signal adjusting circuit and a display panel driving circuit are disclosed. The signal adjusting circuit includes an input terminal, a control terminal, an output terminal, a selection module and a delay module. The selection module is configured to selectively transfer an input signal received via the input terminal to the output terminal depending on an indication signal received via the control terminal. The delay module is configured to delay the input signal received from the selection module by an amount of time and transfer the delayed input signal to the output terminal. The display panel driving circuit includes one or more signal adjusting circuits to adjust periodic output enable pulses that enable outputting of gate scan pulses.