Patents by Inventor Zhijun Qu
Zhijun Qu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230007773Abstract: A cable assembly, a signal transmission structure, and an electronic device are provided. The signal transmission structure includes a circuit board (2), a chip (1), and a cable assembly (3). The chip (1) is assembled on one side of the circuit board (2), and the cable assembly (3) is assembled on the other side of the circuit board (2). The cable assembly (3) includes a cable (31), and the circuit board (2) includes a plurality of conductive holes (22). The chip (1) is electrically connected to the cable (31) of the cable assembly (3) by using the conductive hole (22), to transmit a signal of the chip (1) by using the cable (31). In this technical solution, wires do not need to be disposed in a large area inside the circuit board (2).Type: ApplicationFiled: September 12, 2022Publication date: January 5, 2023Inventors: Guodong Zhang, Chong Chen, Jian Zhang, Shaoyong Xiang, Zhijun Qu, Changxing Sun
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Patent number: 11387226Abstract: This application discloses a chip power supply system, a chip, a PCB, and a computer device. The chip power supply system includes a first printed circuit board (PCB), a chip, a power controller, and an inductor module. The first PCB includes N vias, first ends of the N vias are located at a top layer of the PCB, and second ends of the N vias are located at a bottom layer of the first PCB. The chip is coupled to the top layer of the first PCB through N power supply contacts and the first ends of the N vias. The inductor module is coupled to the chip through M power supply contacts and the second ends of M vias of the N vias. The power controller is coupled to the inductor module through the first PCB, and the power controller is configured to control the inductor module to supply power to the chip.Type: GrantFiled: November 5, 2020Date of Patent: July 12, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Yadong Bai, Zhijun Qu, Changxing Sun, Haitao Han
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Publication number: 20210143141Abstract: This application discloses a chip power supply system, a chip, a PCB, and a computer device. The chip power supply system includes a first printed circuit board (PCB), a chip, a power controller, and an inductor module. The first PCB includes N vias, first ends of the N vias are located at a top layer of the PCB, and second ends of the N vias are located at a bottom layer of the first PCB. The chip is coupled to the top layer of the first PCB through N power supply contacts and the first ends of the N vias. The inductor module is coupled to the chip through M power supply contacts and the second ends of M vias of the N vias. The power controller is coupled to the inductor module through the first PCB, and the power controller is configured to control the inductor module to supply power to the chip.Type: ApplicationFiled: November 5, 2020Publication date: May 13, 2021Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Yadong Bai, Zhijun Qu, Changxing Sun, Haitao Han
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Publication number: 20200203511Abstract: Methods and designs are provided for a vertical power semiconductor switch having an IGBT-with-built-in-diode bottom-side structure combined with a SJMOS topside structure in such a way as to provide fast switching with low switching losses (MOSFET), low on-resistance at low currents (SJMOS), low on-resistance at high currents (IGBT), and high current-density capability (IGBT).Type: ApplicationFiled: March 3, 2020Publication date: June 25, 2020Applicant: D3 Semiconductor LLCInventors: Thomas E. Harrington, III, Zhijun Qu
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Patent number: 10580884Abstract: Methods and designs are provided for a vertical power semiconductor switch having an IGBT-with-built-in-diode bottom-side structure combined with a SJMOS topside structure in such a way as to provide fast switching with low switching losses (MOSFET), low on-resistance at low currents (SJMOS), low on-resistance at high currents (IGBT), and high current-density capability (IGBT).Type: GrantFiled: March 5, 2018Date of Patent: March 3, 2020Assignee: D3 Semiconductor LLCInventors: Thomas E. Harrington, III, Zhijun Qu
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Publication number: 20200026517Abstract: A semiconductor device comprises a vertical power device, such as a superjunction MOSFET, an IGBT, a diode, and the like, and a surface device that comprises one or more lateral devices that are electrically active along a top surface of the semiconductor device.Type: ApplicationFiled: September 10, 2018Publication date: January 23, 2020Applicant: D3 Semiconductor, LLCInventors: Thomas E. Harrington, III, Zhijun Qu
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Patent number: 10134890Abstract: A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.Type: GrantFiled: October 17, 2017Date of Patent: November 20, 2018Assignee: D3 Semiconductor LLCInventors: Thomas E. Harrington, III, John V. Spohnheimer, Zhijun Qu
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Publication number: 20180277673Abstract: A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.Type: ApplicationFiled: October 17, 2017Publication date: September 27, 2018Inventors: Thomas E. Harrington, III, John V. Spohnheimer, Zhijun Qu
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Publication number: 20180261691Abstract: Methods and designs are provided for a vertical power semiconductor switch having an IGBT-with-built-in-diode bottom-side structure combined with a SJMOS topside structure in such a way as to provide fast switching with low switching losses (MOSFET), low on-resistance at low currents (SJMOS), low on-resistance at high currents (IGBT), and high current-density capability (IGBT).Type: ApplicationFiled: March 5, 2018Publication date: September 13, 2018Applicant: D3 Semiconductor LLCInventors: Thomas E. Harrington, III, Zhijun Qu
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Patent number: 10074735Abstract: A semiconductor device comprises a vertical power device, such as a superjunction MOSFET, an IGBT, a diode, and the like, and a surface device that comprises one or more lateral devices that are electrically active along a top surface of the semiconductor device.Type: GrantFiled: September 1, 2017Date of Patent: September 11, 2018Assignee: D3 Semiconductor LLCInventors: Thomas E. Harrington, III, Zhijun Qu
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Publication number: 20180012981Abstract: A semiconductor device comprises a vertical power device, such as a superjunction MOSFET, an IGBT, a diode, and the like, and a surface device that comprises one or more lateral devices that are electrically active along a top surface of the semiconductor device.Type: ApplicationFiled: September 1, 2017Publication date: January 11, 2018Applicant: D3 Semiconductor LLCInventors: Thomas E. Harrington, III, Zhijun Qu
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Patent number: 9806186Abstract: A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.Type: GrantFiled: October 2, 2015Date of Patent: October 31, 2017Assignee: D3 Semiconductor LLCInventors: Thomas E. Harrington, III, John V. Spohnheimer, Zhijun Qu
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Patent number: 9755058Abstract: A semiconductor device comprises a vertical power device, such as a superjunction MOSFET, an IGBT, a diode, and the like, and a surface device that comprises one or more lateral devices that are electrically active along a top surface of the semiconductor device.Type: GrantFiled: February 26, 2016Date of Patent: September 5, 2017Assignee: D3 Semiconductor LLCInventors: Thomas E. Harrington, III, Zhijun Qu
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Publication number: 20170098705Abstract: A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.Type: ApplicationFiled: October 2, 2015Publication date: April 6, 2017Inventors: Thomas E. Harrington, III, John V. Spohnheimer, Zhijun Qu
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Publication number: 20160254373Abstract: A semiconductor device comprises a vertical power device, such as a superjunction MOSFET, an IGBT, a diode, and the like, and a surface device that comprises one or more lateral devices that are electrically active along a top surface of the semiconductor device.Type: ApplicationFiled: February 26, 2016Publication date: September 1, 2016Applicant: D3 Semiconductor LLCInventors: Thomas E. Harrington, III, Zhijun Qu
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Patent number: 8908712Abstract: An access device, a system and a method for implementing service configuration are disclosed. The method includes: identifying, by an access device AN, an operation mode of a CPE according to a result of a handshake negotiation performed between the line port of the access device CN and the CPE, and selecting a corresponding preset service template according to the operation mode of the CPE, and then configuring the line port according to the service template selected, thereby implementing the self adaptation of the ATM mode and PTM mode of the CPE. With the technical solution of the invention, when VDSL2 service is provided, the service may automatically access subscribers of ADSL ATM mode and subscribers of VDSL PTM mode simultaneously, and an automatic configuration and management may be realized for all the service configurations in different modes, and thus the operation complexity may be simplified, and the operation cost may be lowered.Type: GrantFiled: June 25, 2009Date of Patent: December 9, 2014Assignee: Huawei Technologies Co., Ltd.Inventor: Zhijun Qu
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Patent number: 8830674Abstract: The present disclosure discloses a cooling system and an electronic device. The cooling system is configured to cool a circuit board assembly in an orthogonal architecture, where the circuit board assembly is arranged inside a cabinet. The cooling system includes: a first cooling air duct that allows air to flow from the front area of the cabinet corresponding to the region of the circuit board assembly into the cabinet and flow through the front portion of the circuit board assembly, then be distributed into two lateral sides of the circuit board assembly, and be discharged out of the cabinet; and a second cooling air duct that allows air to flow from the front area of the cabinet corresponding to one end of the circuit board assembly into the cabinet and through the rear portion of the circuit board assembly, and then be discharged out of the cabinet.Type: GrantFiled: July 12, 2012Date of Patent: September 9, 2014Assignee: Huawei Technologies Co., Ltd.Inventor: Zhijun Qu
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Publication number: 20130107452Abstract: The present disclosure discloses a cooling system and an electronic device. The cooling system is configured to cool a circuit board assembly in an orthogonal architecture, where the circuit board assembly is arranged inside a cabinet. The cooling system includes: a first cooling air duct that allows air to flow from the front area of the cabinet corresponding to the region of the circuit board assembly into the cabinet and flow through the front portion of the circuit board assembly, then be distributed into two lateral sides of the circuit board assembly, and be discharged out of the cabinet; and a second cooling air duct that allows air to flow from the front area of the cabinet corresponding to one end of the circuit board assembly into the cabinet and through the rear portion of the circuit board assembly, and then be discharged out of the cabinet.Type: ApplicationFiled: July 12, 2012Publication date: May 2, 2013Applicant: Huawei Technologies Co., Ltd.Inventor: Zhijun Qu
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Patent number: 7756147Abstract: The present invention provides a VLAN-based data packet transmission method and an Ethernet bridge device. The method includes: learning a member port corresponding to a VLAN according to a data packet received by an Ethernet bridge device, and storing a correspondence between a VLAN and the learnt member port; and forwarding the data packet by the Ethernet bridge device according to the correspondence between each VLAN and its member port that is stored.Type: GrantFiled: January 29, 2008Date of Patent: July 13, 2010Assignee: Huawei Technologies Co., Ltd.Inventors: Shifa Zhang, Zhijun Qu, Wumao Chen, Qiao Li
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Publication number: 20090257436Abstract: An access device, a system and a method for implementing service configuration are disclosed. The method includes: identifying, by an access device AN, an operation mode of a CPE according to a result of a handshake negotiation performed between the line port of the access device CN and the CPE, and selecting a corresponding preset service template according to the operation mode of the CPE, and then configuring the line port according to the service template selected, thereby implementing the self adaptation of the ATM mode and PTM mode of the CPE. With the technical solution of the invention, when VDSL2service is provided, the service may automatically access subscribers of ADSL ATM mode and subscribers of VDSL PTM mode simultaneously, and an automatic configuration and management may be realized for all the service configurations in different modes, and thus the operation complexity may be simplified, and the operation cost may be lowered.Type: ApplicationFiled: June 25, 2009Publication date: October 15, 2009Applicant: Huawei Technologies Co., Ltd.Inventor: Zhijun Qu