Abstract: The epitaxial silicon junction receiving layer of a power semiconductor device is formed of upper and lower layers. The lower layer has a resistivity of more than that of the upper layer and a thickness of more than that of the upper layer. The total thickness of the two layers is less than that of a single epitaxial layer that would be used for the same blocking voltage. P-N junctions are formed in the upper layer to define a vertical conduction power MOSFET device. The on-resistance is reduced more than 10% without any blocking voltage reduce. The upper epitaxial layer can be either by direct second layer deposition or by ion implantation of a uniform epitaxial layer followed by a driving process.

Abstract: The present invention provides a VLAN-based data packet transmission method and an Ethernet bridge device. The method includes: learning a member port corresponding to a VLAN according to a data packet received by an Ethernet bridge device, and storing a correspondence between a VLAN and the learnt member port; and forwarding the data packet by the Ethernet bridge device according to the correspondence between each VLAN and its member port that is stored. In the invention, the storage space of MAC address table of the Ethernet bridge device only needs to meet the requirement on the MAC address of its local user, thus the requirement of the access convergence network on the storage space of the MAC address table of the Ethernet bridge device may be lowered.

Abstract: A system and method for realizing network synchronization by packet network mainly includes: restoring the clock signal from the superior processing equipment data link of the packet network, and sending it to the subordinate processing equipment; realizing the synchronization of said processing equipment based on said clock signal. It can realize the uniform timing of the whole network and change the IP network without the timing into the synchronous network, which is similarly with the circuit network, with high bandwidth. It can not only provide a circuit simulation service, but also a multi-service with high bandwidth.

Abstract: Embodiments of the present invention provide broadband access equipment and a method for implementing a video service, and the broadband access equipment includes a video service component transmitting stored video service data via the access component of the broadband access equipment to a subscriber terminal according to a request from the subscriber terminal. In accordance with the embodiments of the present invention, the bandwidth demands of video services to an access network and a convergence network are reduced and the bandwidth bottleneck between a backbone network and a convergence network is avoided effectively. The resource management mechanism of an access network and a convergence network is simplified, and the resource management of the access network is simplified. The utilization of network bandwidth is improved, the management of network resources is simplified, and the bottleneck at a video server is avoided.

Abstract: A deep trench super switch device has a plurality of trenches, each of the trenches containing a gate electrode polysilicon layer on top of a plurality of stacked conductive floating polysilicon layers, the remainder of each of the trenches being filled with a nonconductive material.

Abstract: A method and a system for providing clock information synchronization over a packet network, including: a logic tree of clock synchronization is created in the IP packet network to form an IP clock synchronization network; clock information is converted into an IP data message by a clock gateway equipment, the IP data message is transmitted over the IP clock synchronization network by means of the created logic tree of clock synchronization, so that the clock information is transmitted to a packet network equipment. With the inventive methods and systems, clock synchronization information can be provided over the IP packet network without construction of a synchronization timing network, and the costs of network construction can be reduced. Furthermore, the embodiments of the present invention fully unify a data network and a circuit network and thereby make network maintenances easier and more convenient.

Abstract: A deep trench super switch device has a plurality of trenches, each of the trenches containing a gate electrode polysilicon layer on top of a plurality of stacked conductive floating polysilicon layers, the remainder of each of the trenches being filled with a nonconductive material.

Abstract: A process to make a low voltage (under 200 volts) superjunction device employs spaced P type implants into the generally central depth region of an epitaxially formed N layer. The wafer is then placed in a diffusion furnace and the spaced implants are driven upward and downward by 4 to 8 microns to form spaced P pylons in an N type epitaxial body. MOSgated structures are then formed atop each of the P pedestals. The total P charge of each pedestal is at least partially matched to the total N charge of the surrounding epitaxial material. The initial implant may be sandwiched between two discrete epitaxial layers.

Abstract: The termination of a MOSgated device is formed by a trench bevel which surrounds the active device area. The trench bevel has flat walls which extend into and through the epitaxial layer containing the active area which has a lateral extend equal to or less than the thickness of the epitaxial layer. The surface of the bevel is coated with a resistive film, preferably, an amorphous silicon which connects the device source to the device drain to cause the electric field in the epitaxial silicon to the linearly distributed over the length of the bevel.

Abstract: The P type pylons in a superjunction device have an increased concentration at their top to modify charge balance, such that the top of the P regions are not fully depleted during blocking voltage operation, while the remainder of the P type pylons are in charge balance with the surrounding N body region. Avalanche current can then be diverted to the central portion of the P body (for N-channel device) channel region at the top of the pylon and away from the Rb′ under the source to increase ruggedness (turn on of the parasitic bipolar transistor due to avalanche current flow through Rb′) with very little sacrifice of breakdown voltage due to the increased concentration at the top of the pylons.

Abstract: A process to make a low voltage (under 200 volts) superjunction device employs spaced P type implants into the generally central depth region of an epitaxially formed N layer. The wafer is then placed in a diffusion furnace and the spaced implants are driven upward and downward by 4 to 8 microns to form spaced P pylons in an N type epitaxial body. MOSgated structures are then formed atop each of the P pedestals. The total P charge of each pedestal is at least partially matched to the total N charge of the surrounding epitaxial material. The initial implant may be sandwiched between two discrete epitaxial layers.

Abstract: The termination of a MOSgated device is formed by a trench bevel which surrounds the active device area. The trench bevel has flat walls which extend into and through the epitaxial layer containing the active area which has a lateral extend equal to or less than the thickness of the epitaxial layer. The surface of the bevel is coated with a resistive film, preferably, an amorphous silicon which connects the device source to the device drain to cause the electric field in the epitaxial silicon to the linearly distributed over the length of the bevel.

Abstract: A termination structure for a superjunction device on which the net charge between P pylons in an N− termination region is intentionally unbalanced and is negative. The P pylons in the termination area are further non-uniformly located relative to those in the active area. A field ring which is an extension of the source electrode terminates at a radial mid point of the termination region.

Abstract: The epitaxial silicon junction receiving layer of a power semiconductor device is formed of upper and lower layers. The lower layer has a resistivity of more than that of the upper layer and a thickness of more than that of the upper layer. The total thickness of the two layers is less than that of a single epitaxial layer that would be used for the same blocking voltage. P-N junctions are formed in the upper layer to define a vertical conduction power MOSFET device. The on-resistance is reduced more than 10% without any blocking voltage reduce. The upper epitaxial layer can be either by direct second layer deposition or by ion implantation of a uniform epitaxial layer followed by a driving process.

Abstract: A termination structure for a superjunction device on which the net charge between P pylons in an N− termination region is intentionally unbalanced and is negative. The P pylons in the termination area are further non-uniformly located relative to those in the active area. A field ring which is an extension of the source electrode terminates at a radial mid point of the termination region.