Abstract: System and method for driving a plurality of cold-cathode fluorescent lamps. The system includes a subsystem configured to receive at least a DC voltage and generate a first AC voltage in response to at least the DC voltage, a power converter configured to receive the first AC voltage and convert the first AC voltage to at least a second AC voltage, and a plurality of current balancing devices. Each of the plurality of current balancing devices is configured to receive two currents and balance the two currents. The power converter and the plurality of current balancing devices are capable of being directly or indirectly coupled to a plurality of cold-cathode fluorescent lamps.

Abstract: System and method for providing switching to power regulators. According to an embodiment, the present invention provides system for providing switching. The system includes a first voltage supply that is configured to provide a first voltage. The system also includes a second voltage supply that is configured to provide a second voltage. The second voltage being independent from the first voltage. The system additionally includes a controller component that is electrically coupled to the first voltage supply. For example, the controller component being configured to receive at least a first input signal and to provide at least a first output signal. Additionally, the system includes a gate driver component that is electrically coupled to the second voltage supply. The gate driver component is configured to receive at least the first output signal and generated a second output signal in response to at least the second voltage and the first output signal.

Abstract: A system and method for power-on reset and under-voltage lockout schemes. The system includes a first transistor, which includes a first gate, a first terminal, and a second terminal, the second terminal being biased to a predetermined voltage. The system includes a second transistor, which include a second gate, a third terminal, and a fourth terminal, the third terminal being configured to receive an input voltage. The system includes a first resistor that is associated with a first resistance. The first resistor includes a fifth terminal and a sixth terminal, the fifth terminal being configured to receive the input voltage. The system includes a second resistor that is associated with a second resistance. The second resistor includes a seventh terminal and an eighth terminal, the seventh terminal being coupled to the sixth terminal. The system includes a first Zener diode that is associated with a first Zener voltage.

Abstract: A system and method for power-on reset and under-voltage lockout schemes. The system includes a first transistor, which includes a first gate, a first terminal, and a second terminal, the second terminal being biased to a predetermined voltage. The system includes a second transistor, which include a second gate, a third terminal, and a fourth terminal, the third terminal being configured to receive an input voltage. The system includes a first resistor that is associated with a first resistance. The first resistor includes a fifth terminal and a sixth terminal, the fifth terminal being configured to receive the input voltage. The system includes a second resistor that is associated with a second resistance. The second resistor includes a seventh terminal and an eighth terminal, the seventh terminal being coupled to the sixth terminal. The system includes a first Zener diode that is associated with a first Zener voltage.

Abstract: A system and method for driving a bipolar junction transistor is provided. The system includes a first transistor including a first gate, a first terminal, and a second terminal. The first gate is configured to receive a first control signal. Additionally, the system includes a second transistor including a second gate, a third terminal, and a fourth terminal. The second gate is configured to receive a second control signal. Moreover, the system includes a first resistor including a fifth terminal and a sixth terminal. The fifth terminal is connected to the first terminal, and the sixth terminal is biased to a first predetermined voltage. The fourth terminal is biased to a second predetermined voltage. The second terminal and the third terminal are connected at a node, and the node is connected to a base for a bipolar junction transistor.

Abstract: System and method for protecting a power converter. The system includes a first comparator configured to receive a threshold signal and a first signal and to generate a comparison signal. The first signal is a sum of a second signal and a third signal, and the third signal is associated with an input current for a power converter. Additionally, the system includes a pulse-width-modulation generator configured to receive the comparison signal and generate a modulation signal in response to the comparison signal, and a switch configured to receive the modulation signal and control the input current for the power converter. An amplitude for the first signal becomes larger if an amplitude for the input voltage becomes larger. The second signal is generated by receiving an input voltage for the power converter, converting the received input voltage to a fourth signal, and converting the fourth signal to the second signal.

Abstract: System and method for protecting a power converter. The system includes a compensation system configured to receive an input signal and generate a control signal, a cycle threshold generator configured to receive the control signal and generate a cycle threshold, and a comparator configured to receive the cycle threshold and a feedback signal and generate a comparison signal. Additionally, the system includes a pulse-width-modulation generator configured to receive the comparison signal and generate a modulation signal in response to the comparison signal, and a switch configured to receive the modulation signal and control an input current for a power converter. The input current is associated with an output power for the power converter. The cycle threshold corresponds to a threshold power level for the output power. The threshold power level is constant, decreases, or increases with respect to the input signal.

Abstract: System and method for protecting an integrated circuit. The system includes a first transistor coupled to a first voltage and a second voltage, a second transistor coupled to the gate of the first transistor and the first voltage, a third transistor coupled to the gate of the second transistor and the first voltage, and a capacitor coupled to the gate of the second transistor and the second voltage. The first voltage is provided to the integrated circuit, the gate of the third transistor is configured to receive a first control signal, the gate of the second transistor is configured to receive a second control signal, and the second control signal is capable of turning off the second transistor a time period after the third transistor is turned off.

Abstract: System and method for providing frequency control to a power converter. The system includes a pseudorandom signal generator configured to generate a digital signal. The digital signal is associated with at least an N-bit datum, and N is a positive integer. Additionally, the system includes a digital-to-analog converter configured to receive the digital signal and generate a first control signal, an output signal generator configured to receive the first control signal and generate at least a first output signal associated with a frequency, and a pulse-width-modulation generator configured to receive at least the first output signal. The N-bit datum represents a pseudorandom number.

Abstract: System and method for providing frequency control to a power converter. The system includes a controller configured to receive a load signal and generate a first control signal. The load signal indicates an output load for a power converter. Additionally, the system includes a signal generator configured to receive the first control signal and generates at least a first output signal. The first output signal is associated with a first signal strength and a first frequency. The first frequency is inversely proportional to a sum of a first time period, a second time period, and a third time period. The first signal strength increases with the time during the first time period, the first signal strength decreases with the time during the second time period, and the first signal strength is constant with respect to the time during the third time period.

Abstract: System and method for protecting a power converter. The system includes a compensation system configured to receive an input signal and generate a control signal, a cycle threshold generator configured to receive the control signal and generate a cycle threshold, and a comparator configured to receive the cycle threshold and a feedback signal and generate a comparison signal. Additionally, the system includes a pulse-width-modulation generator configured to receive the comparison signal and generate a modulation signal in response to the comparison signal, and a switch configured to receive the modulation signal and control an input current for a power converter. The input current is associated with an output power for the power converter. The cycle threshold corresponds to a threshold power level for the output power. The threshold power level is constant, decreases, or increases with respect to the input signal.

Abstract: System and method for protecting a power converter. The system includes a compensation system configured to receive an input signal and generate a control signal, a cycle threshold generator configured to receive the control signal and generate a cycle threshold, and a comparator configured to receive the cycle threshold and a feedback signal and generate a comparison signal. Additionally, the system includes a pulse-width-modulation generator configured to receive the comparison signal and generate a modulation signal in response to the comparison signal, and a switch configured to receive the modulation signal and control an input current for a power converter. The input current is associated with an output power for the power converter. The cycle threshold corresponds to a threshold power level for the output power. The threshold power level is constant, decreases, or increases with respect to the input signal.

Abstract: An SCR (68) for protecting an integrated circuit (62) against ESD events is provided having a trigger voltage which is automatically adjusted to different trigger voltage levels in response to power being applied to the integrated circuit (62). An enhancement-type P-channel transistor (78) is provided for determining the trigger voltage. When operating power is not being applied to the integrated circuit (62), the P-channel transistor (78) threshold voltage determines the voltage at which the SCR (68) is triggered. When operating power is being applied to the integrated circuit (62), the operating voltage is applied to the gate of the P-channel transistor (78), and then the operating voltage and the threshold voltage for the P-channel transistor (78) determine the trigger voltage of the SCR (68). Then, a PNP and NPN transistor pair (76, 80) that form the SCR (68) are latched to shunt the protected signal path (69) to ground.

Abstract: The present invention provides a high efficiency ESD circuit that requires less space through uniform activation of multiple emitter fingers of a transistor structure containing an integral Zener diode. The Zener diode is able to lower the protection circuit trigger threshold from around 18 volts to around 7 volts. This method minimizes series impedance of the signal path, thereby rendering an NPN structure that is particularly well suited for protecting bipolar and CMOS input and output buffers. The ESD circuit of the present invention provides a relatively low shunt capacitance (typically <0.5 pF) and series resistance (typically <0.5 ohm) that are desirable for input and output circuits of present and future contemplated generations of sub-micron bipolar/BiCMOS circuit processes.

Abstract: The invention provides a Bipolar structure such as a silicon controlled rectifier (SCR) that exhibits advantageously low triggering and holding voltages for use in high speed (e.g., 900 MHz->2 GHz) submicron ESD protection circuits for Bipolar/BiCMOS circuits. The Bipolar structure features a low shunt capacitance and a low series resistance on the input and output pins, allowing for the construction of ESD protection circuits having small silicon area and little to no impedance added in the signal path. In a preferred aspect of the invention, the SCR is assembled in the N-well of the Bipolar/BiCMOS device, as opposed to the P-substrate, as is customary in the prior art. A preferred aspect of the invention utilizes a Zener diode in combination with a resistor to control BSCR operation through the NPN transistor.

Abstract: The invention provides a Bipolar structure such as a silicon controlled rectifier (SCR) that exhibits advantageously low triggering and holding voltages for use in high speed (e.g., 900 MHz->2 GHz) submicron ESD protection circuits for Bipolar/BiCMOS circuits. The Bipolar structure features a low shunt capacitance and a low series resistance on the input and output pins, allowing for the construction of ESD protection circuits having small silicon area and little to no impedance added in the signal path. In a preferred aspect of the invention, the SCR is assembled in the N-well of the Bipolar/BiCMOS device, as opposed to the P-substrate, as is customary in the prior art. A preferred aspect of the invention utilizes a Zener diode in combination with a resistor to control BSCR operation through the PNP transistor.