Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. The first semiconductor structure or the second semiconductor structure further includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first peripheral circuit and the second peripheral circuit are stacked over one another.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit.

Abstract: Semiconductor devices, fabrication methods thereof and memory systems are provided. In one aspect, a semiconductor device includes chips and a bonding dielectric layer. The chips are stacked along a thickness direction of the chips. The bonding dielectric layer is located between two adjacent ones of the chips. The bonding dielectric layer at least includes a first material and a second material, and thermal conductivity of the second material is greater than thermal conductivity of the first material.

Abstract: A memory, a controlling method thereof, a memory system and an electronic device are disclosed. The memory can include a semiconductor layer and a memory array disposed on the semiconductor layer. The memory array can include a plurality of memory strings connected with the same bit line. Each memory string can include a memory cell and a select cell connected on at least one side of the memory cell. The select cell can include a first kind of transistors with a first threshold voltage and a second kind of transistors with a second threshold voltage. The first kind of transistors can be connected with the second kind of transistors. The first threshold voltage can be different from the second threshold voltage. Different memory strings can be controlled to be on or off to realize selective controlling functions for a plurality of memory strings connected with the same bit line.

Abstract: A memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a drain-select gate (DSG) cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.

Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.

Abstract: Aspects of the disclosure provide a semiconductor device including a first die. The first die includes a first stack of layers including a semiconductor layer on a backside of the first die. A second stack of layers is formed that includes gate layers and first insulating layers alternatingly stacked on a face side of the first die. The face side is opposite to the backside. A vertical structure includes a first portion disposed in the first stack of layers and a second portion extending through the second stack of layers. The first portion has a different dimension than the second portion in a direction parallel to a main surface of the first die.

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure including interleaved conductive layers and dielectric layers along a first direction, a semiconductor layer over the stack structure, and a channel structure extending through the stack structure and in contact with the semiconductor layer. The channel structure includes a semiconductor channel extending along the first direction and a composite dielectric film surrounding the semiconductor channel. The semiconductor channel includes a first portion extending through at least one of the conductive layers. The at least one of the conductive layers is between the semiconductor layer and another of the conductive layers. The first portion includes a doped portion.

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: In an example, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending vertically through the memory stack, a semiconductor layer over the memory stack and electrically connected to the channel structure, and a source contact over the memory stack and electrically connected to the semiconductor layer. The source contact and the memory stack are disposed on opposite sides of the semiconductor layer.

Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.

Abstract: In certain aspects, a memory device includes a first semiconductor structure. The first semiconductor structure includes a vertical transistor including a semiconductor body extending in a first direction, a plurality of storage units stacked in the first direction and coupled to a first end of the vertical transistor, and a plurality of plate lines each extending perpendicularly to the first direction and coupled to a respective one of the storage units.

Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes sequentially forming a first and a second dielectric stacks on a substrate. The first dielectric stack includes a first and a second dielectric layers alternatingly stacked in a first direction perpendicular to the substrate. The second dielectric stack comprises a third and a fourth dielectric layers stacked in the first direction. The method further includes forming an etch-stop layer on the second dielectric stack and forming a gate line slit (GLS) trench spacer to cover a sidewall of the etch-stop layer. The method further includes replacing the fourth and the second dielectric layers with conductive layers through a GLS opening to form a top select gate (TSG) film stack and a film stack of alternating conductive and dielectric layers, respectively.

Abstract: A method for performing an erasing operation on a memory device is provided. The memory device includes a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar, and a bit line formed above the drain cap. A first positive voltage bias is applied to the bottom select gate. A second positive voltage bias is applied to the plate line. The first positive voltage bias to the bottom select gate is reduced. A negative voltage bias is applied to the source line.

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

Abstract: Methods for thermal treatment on a semiconductor device is disclosed. One method includes obtaining a pattern of a treatment area having amorphous silicon, aligning a laser beam with the treatment area, the laser beam in a focused laser spot having a spot area equal to or greater than the treatment area, and performing a laser anneal on the treatment area by emitting the laser beam towards the treatment area for a treatment period.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate, a first tier of conductor layers of a first length comprising a first plurality of conductor layers extending along a first direction over the substrate. The first direction is substantially parallel to a top surface of the substrate. In some embodiments, the memory device also includes at least one connection portion conductively connecting two or more conductor layers of the first tier, and a first metal contact via conductively shared by connected conductor layers of the first tier and connected to a first metal interconnect.

Abstract: Semiconductor devices, manufacturing methods thereof and memory systems are provided. In one aspect, a semiconductor device includes: channel structures. wherein at least one of the channel structures includes a first side portion and a second side portion arranged along a first direction and a connection portion connected to first end portions of the first side portion and the second side portion in a second direction; first dielectric layers located on surfaces of the first side portion and the second side portion that are opposite to each other; and gate layers located on surfaces of the first dielectric layers and extending along a third direction, wherein the first direction, the second direction, and the third direction intersect with each other.

Abstract: A memory, a controlling method thereof, a memory system and an electronic device are disclosed. The memory can include a semiconductor layer and a memory array disposed on the semiconductor layer. The memory array can include a plurality of memory strings connected with the same bit line. Each memory string can include a memory cell and a select cell connected on at least one side of the memory cell. The select cell can include a first kind of transistors with a first threshold voltage and a second kind of transistors with a second threshold voltage. The first kind of transistors can be connected with the second kind of transistors. The first threshold voltage can be different from the second threshold voltage. Different memory strings can be controlled to be on or off to realize selective controlling functions for a plurality of memory strings connected with the same bit line.

Abstract: A memory device includes a stack structure and a first beam structure. The memory device includes array regions and an intermediate region arranged between the array regions in a first lateral direction. The stack structure includes a first block and a second block arranged in a second lateral direction. Each of the first block and the second block includes a wall-structure region. In the intermediate region, the wall-structure regions of the first block and the second block are separated by a staircase structure. The first beam structure is located in the intermediate region and extends along the second lateral direction. The first beam structure is connected to the wall-structure regions of the first block and the second block. The first beam structure includes first dielectric layers and electrode layers that are alternately stacked.