Patents by Inventor Zhiliang XIA

Zhiliang XIA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210375368
    Abstract: Aspects of the disclosure provide a method for data erase in a memory device. The method includes providing first erase carriers from a body portion for the memory cell string, during an erase operation in a memory cell string. The first erase carriers flow in a first direction from a source side of the memory cell string to a drain side of the memory cell string. Further, the method includes providing second erase carriers from a junction at the drain side of the memory cell string. The second erase carriers flow in a second direction from the drain side of the memory cell string to the source side of the memory cell string. Then, the method includes injecting the first erase carriers and the second erase carriers to charge storage portions of the memory cells in the memory cell string.
    Type: Application
    Filed: December 7, 2020
    Publication date: December 2, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Lei LIU, Wenxi ZHOU, Zhiliang XIA
  • Publication number: 20210375915
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, an N-type doped semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer, a conductive layer in contact with upper ends of the plurality of channel structures, at least part of which is on the N-type doped semiconductor layer, and a source contact above the memory stack and in contact with the N-type doped semiconductor layer.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 2, 2021
    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Kun Zhang, Ziqun Hua, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
  • Publication number: 20210375828
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, an N-type doped semiconductor layer on the sacrificial layer, and a dielectric stack on the N-type doped semiconductor layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the N-type doped semiconductor layer is formed. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate and the sacrificial layer are removed to expose an end of the channel structure. Part of the channel structure abutting the N-type doped semiconductor layer is replaced with a semiconductor plug.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 2, 2021
    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Kun Zhang, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
  • Publication number: 20210375912
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, an N-type doped semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer, and a source contact above the memory stack and in contact with the N-type doped semiconductor layer. An upper end of each of the plurality of channel structures is flush with or below a top surface of the N-type doped semiconductor layer.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 2, 2021
    Inventors: Kun Zhang, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
  • Publication number: 20210375900
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, a first stop layer on the sacrificial layer, an N-type doped semiconductor layer on the first stop layer, and a dielectric stack on the N-type doped semiconductor layer are sequentially formed. A plurality of channel structures each extending vertically through the dielectric stack and the N-type doped semiconductor layer are formed, stopping at the first stop layer. The dielectric stack is replaced with a memory stack, such that each of the plurality of channel structures extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate, the sacrificial layer, and the first stop layer are sequentially removed to expose an end of each of the plurality of channel structures. A conductive layer is formed in contact with the ends of the plurality of channel structures.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 2, 2021
    Inventors: Kun Zhang, Ziqun Hua, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
  • Publication number: 20210366917
    Abstract: Memory device includes a bottom-select-gate (BSG) structure including cut slits vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. A first gate-line slit is between first and second finger regions and includes gate-line sub-slits. The first finger region is divided into a first string region and a second string region by a first cut-slit, formed in the first finger region along a second lateral direction and further extended into at least the second finger region along the first lateral direction. At least one BSG defined by the first cut-slit is located in at least the second finger region to connect to cell strings in the first string region through an inter-portion between adjacent gate-line sub-slits.
    Type: Application
    Filed: June 12, 2020
    Publication date: November 25, 2021
    Inventors: Zhongwang SUN, Rui SU, Zhong ZHANG, Wenxi ZHOU, Zhiliang XIA
  • Publication number: 20210367051
    Abstract: Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.
    Type: Application
    Filed: July 1, 2020
    Publication date: November 25, 2021
    Inventors: Zhongwang SUN, Zhong ZHANG, Lei LIU, Wenxi ZHOU, Zhiliang XIA
  • Patent number: 11183575
    Abstract: Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 23, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhongwang Sun, Zhong Zhang, Lei Liu, Wenxi Zhou, Zhiliang Xia
  • Publication number: 20210358945
    Abstract: In a method for fabricating a semiconductor device, an initial stack is formed. The initial stack is formed of sacrificial layers and insulating layers that are alternatingly disposed over a substrate, and includes a first connection region, a first array region, and a second connection region that are disposed sequentially. A first initial staircase is formed in the first connection region and formed in a first group of sacrificial layers and insulating layers. A first top select gate staircase is formed in the second connection region, and formed in a second group of sacrificial layers and insulating layers. An etching process is subsequently performed in the first connection region to shift the first initial staircase toward the substrate along a vertical direction perpendicular to the substrate so as to form a first bottom select gate staircase.
    Type: Application
    Filed: December 7, 2020
    Publication date: November 18, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhong ZHANG, Zhongwang SUN, Wenxi ZHOU, Zhiliang XIA
  • Patent number: 11177270
    Abstract: Embodiments of a three-dimensional (3D) memory device are provided. A method for forming a 3D memory device is disclosed. A dielectric stack including interleaved sacrificial layers and dielectric layers is formed over a substrate. Channel holes and contact holes are formed through the dielectric stack. The contact holes extend vertically into the substrate and are each surrounded by channel holes of nominally equal lateral distances to the respective contact hole in a plan view. A channel structure is formed in each of the channel holes. A memory stack having interleaved conductive layers and dielectric layers is formed by replacing, through the contact holes, the sacrificial layers in the dielectric stack with the conductive layers. A spacer is formed along a sidewall of each of the contact holes to cover the conductive layers of the memory stack. A contact is formed over the spacer in each of the contact holes. The contact is electrically connected to a common source of the channel structures.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: November 16, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Wenyu Hua, Fandong Liu, Zhiliang Xia
  • Patent number: 11171154
    Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes gate layers and insulating layers that are stacked alternatingly along a direction perpendicular to a substrate of the semiconductor device and form a stack upon the substrate. The semiconductor device includes an array of channel structures that are formed in an array region of the stack. Further, the semiconductor device includes a first staircase formed of a first section of the stack in a connection region upon the substrate, and a second staircase formed of a second section of the stack in the connection region upon the substrate. In addition, the semiconductor device includes a dummy staircase formed of the first section of the stack and disposed between the first staircase and the second staircase in the connection region.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 9, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhong Zhang, Wenxi Zhou, Zhiliang Xia
  • Patent number: 11164633
    Abstract: A memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and one or more peripheral devices on the first substrate. The second semiconductor structure includes a first set of conductive lines electrically coupled with a first set of a plurality of vertical structures and a second set of conductive lines electrically coupled with a second set of the plurality of vertical structures different from the first set of the plurality of vertical structures. The first set of conductive lines are vertically distanced from one end of the plurality of vertical structures and the second set of conductive lines are vertically distanced from an opposite end of the plurality of vertical structures.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 2, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zongliang Huo, Jun Liu, Zhiliang Xia, Li Hong Xiao
  • Publication number: 20210335807
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a P-type doped region of a substrate, an N-type doped semiconductor layer on the P-type doped region, a memory stack including interleaved conductive layers and dielectric layers on the N-type doped semiconductor layer, a channel structure extending vertically through the memory stack and the N-type doped semiconductor layer into the P-type doped region, an N-type doped semiconductor plug extending vertically into the P-type doped region, and a source contact structure extending vertically through the memory stack to be in contact with the N-type doped semiconductor plug.
    Type: Application
    Filed: May 28, 2020
    Publication date: October 28, 2021
    Inventors: Linchun Wu, Shan Li, Zhiliang Xia, Kun Zhang, Wenxi Zhou, Zongliang Huo
  • Publication number: 20210320115
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes an insulating layer, a semiconductor layer, a memory stack including interleaved conductive layers and dielectric layers, a source contact structure extending vertically through the insulating layer from an opposite side of the insulating layer with respect to the semiconductor layer to be in contact with the semiconductor layer, and a channel structure extending vertically through the memory stack and the semiconductor layer into the insulating layer or the source contact structure.
    Type: Application
    Filed: October 29, 2020
    Publication date: October 14, 2021
    Inventors: Linchun Wu, Kun Zhang, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
  • Publication number: 20210320124
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A first polysilicon layer, a dielectric sacrificial layer, a second polysilicon layer, and a dielectric stack are sequentially formed above a substrate. A channel structure extending vertically through the dielectric stack, the second polysilicon layer, and the dielectric sacrificial, and into the first polysilicon layer is formed. An opening extending vertically through the dielectric stack and the second polysilicon layer, and extending vertically into or through the dielectric sacrificial layer to expose part of the dielectric sacrificial layer, and a polysilicon spacer along part of a sidewall of the opening are formed. The dielectric sacrificial layer is replaced, through the opening, with a third polysilicon layer between the first and second polysilicon layers.
    Type: Application
    Filed: January 12, 2021
    Publication date: October 14, 2021
    Inventors: Linchun Wu, Kun Zhang, Wenxi Zhou, Zhiliang Xia
  • Publication number: 20210320120
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a stop layer, a polysilicon layer, a memory stack including interleaved stack conductive layers and stack dielectric layers, and a plurality of channel structures each extending vertically through the memory stack and the polysilicon layer, stopping at the stop layer.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 14, 2021
    Inventors: Linchun Wu, Kun Zhang, Wenxi Zhou, Zhiliang Xia
  • Publication number: 20210320119
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and an insulating structure extending vertically through the memory stack, the first semiconductor layer, and the second semiconductor layer.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 14, 2021
    Inventors: Kun Zhang, Di Wang, Lei Liu, Wenxi Zhou, Zhiliang Xia
  • Publication number: 20210320094
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and a source contact above the memory stack and in contact with the second semiconductor layer.
    Type: Application
    Filed: May 22, 2020
    Publication date: October 14, 2021
    Inventors: Kun Zhang, Linchun Wu, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
  • Publication number: 20210320122
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer above and in contact with the plurality of channel structures, a plurality of source contacts above the memory stack and in contact with the semiconductor layer, a plurality of contacts through the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below and in contact with the source line mesh. A first set of the plurality of contacts are distributed below and in contact with the source line mesh.
    Type: Application
    Filed: September 14, 2020
    Publication date: October 14, 2021
    Inventors: Kun Zhang, Zhong Zhang, Lei Liu, Wenxi Zhou, Zhiliang Xia
  • Publication number: 20210320118
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer above a second semiconductor layer at a first side of a substrate and a dielectric stack on the sacrificial layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the sacrificial layer into the second semiconductor layer is formed. The sacrificial layer is replaced with a first semiconductor layer in contact with the second semiconductor layer. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the first semiconductor layer into the second semiconductor layer. A source contact is formed at a second side opposite to the first side of the substrate to be in contact with the second semiconductor layer.
    Type: Application
    Filed: May 22, 2020
    Publication date: October 14, 2021
    Inventors: Kun Zhang, Linchun Wu, Wenxi Zhou, Zhiliang Xia, Zongliang Huo