Abstract: Aspects of the disclosure provide a semiconductor device including a first die. The first die includes a first stack of layers including a semiconductor layer on a backside of the first die. A second stack of layers is formed that includes gate layers and first insulating layers alternatingly stacked on a face side of the first die. The face side is opposite to the backside. A vertical structure includes a first portion disposed in the first stack of layers and a second portion extending through the second stack of layers. The first portion has a different dimension than the second portion in a direction parallel to a main surface of the first die.

Abstract: In certain aspects, a memory device includes an array of memory cells, a plurality of word lines, and a plurality of slit structures. Each memory cell includes a vertical transistor, and a storage unit coupled to the vertical transistor. The array of memory cells is arranged in rows in a first direction and columns in a second direction. Two adjacent rows of the memory cells are staggered with one another, and two adjacent columns of the memory cells are staggered with one another in a plan view. Each word line extends in the second direction. Each slit structure extends in the second direction and separating two adjacent word lines of the plurality of word lines in the first direction.

Abstract: In certain aspects, a memory device includes a vertical transistor, a storage unit, and a bit line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and in contact with a second terminal. The second terminal is another one of the source and the drain that is formed on one or some sides, but not all sides, of a protrusion of the semiconductor body. The bit line is separated from the channel portion of the semiconductor body by the second terminal.

Abstract: In certain aspects, a memory device includes a vertical transistor including a semiconductor body extending in a first direction, a stack structure including interleaved dielectric layers and conductive layers each extending perpendicularly to the first direction, an electrode layer including a conductive material and coupled to a first end of the semiconductor body, and a storage layer over the electrode layer. The electrode layer and the storage layer extend in the first direction through the stack structure.

Abstract: Methods for thermal treatment on a semiconductor device is disclosed. One method includes obtaining a pattern of a treatment area having amorphous silicon, aligning a laser beam with the treatment area, the laser beam in a focused laser spot having a spot area equal to or greater than the treatment area, and performing a laser anneal on the treatment area by emitting the laser beam towards the treatment area for a treatment period.

Abstract: A three-dimensional (3D) memory device includes interleaved conductive layers and dielectric layers. Edges of the conductive layers and dielectric layers define a plurality of stairs. The 3D memory device may also include a plurality of landing structures each disposed on a respective conductive layer at a respective stair. Each of the landing structures comprises a first layer of a first material and a second layer of a second material. The first layer is over the second layer. The second material is different from the first material.

Abstract: In an example, a method for forming a three-dimensional (3D) memory device is disclosed. A semiconductor layer is formed. A memory stack on the semiconductor is formed. A channel structure extending through the memory stack and the semiconductor layer is formed. An end of the channel structure abutting the semiconductor layer is exposed. A portion of the channel structure abutting the semiconductor layer is replaced with a semiconductor plug.

Abstract: A semiconductor device includes an insulating layer, a conductive layer stacking with the insulating layer, a spacer structure through the conductive layer and in contact with the insulating layer, a contact structure in the spacer structure and extending vertically through the insulating layer, and a channel structure including a semiconductor channel, a portion of the semiconductor channel being in contact with the conductive layer. The contact structure includes a first contact portion and a second contact portion in contact with each other.

Abstract: A three-dimensional (3D) memory device is disclosed. The 3D memory device includes a memory stack, a semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack, and a source contact above the memory stack and in contact with the semiconductor layer. A semiconductor plug, in contact with the semiconductor layer, surrounds an end of one of the channel structures. The source contact is electrically connected with the one of the channel structures. At least a portion of the source contact is buried within the semiconductor layer.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer above a second semiconductor layer at a first side of a substrate and a dielectric stack on the sacrificial layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the sacrificial layer into the second semiconductor layer is formed. The sacrificial layer is replaced with a first semiconductor layer in contact with the second semiconductor layer. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the first semiconductor layer into the second semiconductor layer. A source contact is formed at a second side opposite to the first side of the substrate to be in contact with the second semiconductor layer.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack including interleaved stack conductive layers and stack dielectric layers, a semiconductor layer, a plurality of channel structures each extending vertically through the memory stack into the semiconductor layer, and an insulating structure extending vertically through the memory stack and including a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.

Abstract: A semiconductor device is provided that can include a stack formed of word line layers and insulating layers that are alternatingly stacked over a substrate. A first staircase of a first block can be formed in the stack and extend between first array regions of the first block. A second staircase of a second block can be formed in the stack and extend between second array regions of the second block. The semiconductor device further can have a connection region that is formed in the stack between the first staircase and second staircase.

Abstract: Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.

Abstract: The three-dimensional memory includes a stack structure which includes: a first stack and a second stack, the first stack including control gate layers and first dielectric layers which are stacked alternately, the second stack including top select gate layers and second dielectric layers which are stacked alternately in the same stacking direction; a plurality of channel structures which run though the stack structure and include charge storage layers, the charge storage layers including a plurality of charge storage portions disposed discontinuously in the stacking direction, the charge storage portions being disposed between the adjacent first dielectric layers; and at least one isolation structure which runs through the top select gate layers and is located between the adjacent channel structures.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, and a slit structure. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The slit structure includes a contact including a first contact portion and a second contact portion above the first contact portion and having a different material of the first contact portion. An upper end of the second contact portion of the slit structure is flush with an upper end of the channel local contact.

Abstract: The present disclosure relates to a three-dimensional (3D) memory and a fabrication method thereof. The method includes forming a memory chip on a first substrate, disposing a first semiconductor layer on the memory chip, forming a plurality of first contacts through the first semiconductor layer, forming a first peripheral circuit chip based on the first semiconductor layer, disposing a second semiconductor layer on the first peripheral circuit chip, forming a plurality of second contacts through the second semiconductor layer, and forming a second peripheral circuit chip based on the second semiconductor layer. The first peripheral circuit chip is electrically connected with the memory chip through the plurality of first contacts, and the second peripheral circuit chip is electrically connected with the memory chip through the plurality of first and second contacts.

Abstract: Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. A disclosed 3D memory device can comprise an alternating conductive/dielectric stack on a substrate, a plurality of channel structures in the alternating conductive/dielectric stack, and a plurality of gate line slit (GLS) structures in the alternating conductive/dielectric stack. Each GLS structure can include a plurality of first type GLS portions penetrating the alternating conductive/dielectric stack, and a plurality of second type GLS portions in an upper portion of the alternating conductive/dielectric stack.

Abstract: A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a first angled structure, and a first diameter of the memory film at the bottom portion below the first angled structure is smaller than a second diameter of the memory film at an upper portion above the first angled structure.

Abstract: A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer. A first thickness of the bottom portion of the channel structure is larger than a second thickness of a top portion of the channel structure.

Abstract: A semiconductor device is provided that can include a stack formed of word line layers and insulating layers that are alternatingly stacked over a substrate. A first staircase of a first block can be formed in the stack and extend between first array regions of the first block. A second staircase of a second block can be formed in the stack and extend between second array regions of the second block. The semiconductor device further can have a connection region that is formed in the stack between the first staircase and second staircase.