Abstract: A chip package and a chip packaging method are provided. The package includes: a chip to be packaged, a reinforcing layer and solder bumps. The chip to be packaged includes a first surface and a second surface opposite to each other, the first surface includes a sensing region and first contact pads, and the first contact pads are electrically coupled to the sensing region. The reinforcing layer covers the first surface of the chip to be packaged. The solder bumps are provided on the second surface of the chip to be packaged. The solder bump is electrically connected to the first contact pad and is configured to electrically connect with an external circuit.

Abstract: A package for an image sensing chip is provided, which includes: an image sensing chip comprising a first surface and a second surface opposite to each other, where the first surface is provided with an image sensing region and a contact pad; a through hole extending from the second surface to the contact pad; an electrical connection layer provided along an inner wall of the through hole and extending onto the second surface; a solder mask filling the through hole and covering the electrical connection layer, wherein an opening is formed in the solder mask, and the electrical connection layer is exposed at a bottom of the opening; a guide contact pad covering an inner wall and the bottom of the opening and extending onto the solder mask; and a solder bump located on the guide contact pad.

Abstract: A package-on-package structure of an image sensing chip is provided, which includes: an image sensing chip package, a control chip package and a circuit board. The image sensing chip package and the control chip package are arranged on the same surface of the control chip package in parallel. The image sensing chip package includes a first substrate and an image sensing chip. The control chip package includes a second substrate and a control chip. A second surface of the first substrate is electrically connected to a first region of a first surface of the second substrate, and the circuit board is electrically connected to a second region of the first surface of the second substrate. A package-on-package method for a package-on-package structure is further provided.

Abstract: A method for forming an image sensor package and an image sensor package are provided. The method includes: providing a first substrate and a second substrate which includes a first surface and a second surface opposite to the first surface, and attaching either surface of the first substrate with the first surface of the second substrate with an adhesive layer; forming a groove at the second surface of the second substrate; providing a base which includes a first surface and a second surface opposite to the first surface, where the first surface of the base is provided with a sensing region and multiple contact pads; and attaching the second surface of the second substrate with the first surface of the base, where a cavity is formed between the groove and the base, and the sensing region is located within the cavity.

Abstract: A fingerprint sensing chip packaging method and package are provided. The method includes: providing a cover plate, providing a fingerprint sensing chip, where a fingerprint sensing region and contact pads at periphery of the region are arranged on a front surface of the chip, electrically connecting the contact pads to a back surface of the chip, forming a first conductive structure electrically connected to the contact pads on the back surface of the chip, laminating the front surface of the chip with a back surface of the cover plate, providing a flexible printed circuit, where a second conductive structure is arranged on a back surface of the circuit and an opening is arranged in the circuit, laminating a front surface of the circuit with the back surface of the cover plate, and electrically connecting the first conductive structure to the second conductive structure.

Abstract: A packaging structure and a packaging method are provided. The packaging structure includes: a chip unit, where a first surface of the chip unit includes a sensing region; and an upper cover plate structure, where a first surface of the upper cover plate structure is provided with a groove structure, the first surface of the chip unit is attached with the first surface of the upper cover plate structure, the sensing region is located within a cavity surrounded by the groove structure and the first surface of the chip unit, the upper cover plate structure further includes a second surface opposite to the first surface, and an area of the second surface of the upper cover plate structure is less than an area of the first surface of the upper cover plate structure.

Abstract: Provided are a packaging method and packaging structure for a semiconductor chip. The packaging method comprises: providing a wafer, the wafer being provided with multiple semiconductor chips, each semiconductor chip being provided with a functional area and solder pads arranged on a first surface; providing a protective substrate, multiple support units being provided on the protective substrate, openings being formed on the support units; aligning the solder pads to the openings and facing support units provided on the protective substrate to the first surface of the wafer, and pressing together the wafer and the protective substrate. The packaging method effectively prevents the support units from generating stress that acts on the solder pads in a subsequent reliability test, thus preventing cases of the solder pad being damaged or split into layers.

Abstract: A semiconductor chip package and a semiconductor chip packaging method are provided. The package includes: a semiconductor chip having a functional region, a protective substrate located on one side of the semiconductor chip and covering the functional region, and a support unit located between the protective substrate and the semiconductor chip and enclosing the functional region. The support unit includes an outer support member and an inner support member located inside the outer support member. A receiving cavity is formed between the inner support member, the semiconductor chip and the protective substrate. A hollow cavity is formed between the inner support member, the outer support member, the semiconductor chip and the protective substrate. The inner support member is provided with at least one first ventilating structure, through which the receiving cavity is in communication with the hollow cavity.

Abstract: A packaging structure and a packaging method are provided. The packaging structure includes a substrate, a circuit wiring layer arranged on the substrate, a conductive bump arranged on the circuit wiring layer, and a semiconductor chip flip-chip mounted over the substrate. A functional area and a pad surrounding the functional area are arranged on a first surface of the semiconductor chip facing the substrate, and the pad is electrically connected to the conductive bump. The packaging structure further includes a sealing layer arranged on the substrate and surrounding the semiconductor chip, and a blocking structure arranged on the substrate. The blocking structure surrounds the functional area to block a material of the sealing layer from overflowing into the functional area.

Abstract: A semiconductor device and a manufacture method of the semiconductor device are provided. In the semiconductor device, a back surface of a substrate is covered with a first insulating layer, where the first insulating layer covers the bottom and the sidewall of a through hole and the back surface of the substrate outside the through hole. The first insulating layer outside the through hole is covered with a second insulating layer. When etching the first insulating layer at the bottom of the through hole, although an etching speed for a region outside the through hole is greater than an etching speed for the bottom of the through hole, the first insulating layer outside the through hole is protected from being over-etched by the second insulating layer, which improves reliability of the device.

Abstract: A chip package and a chip packaging method are provided. A MEMS chip and an ASIC chip are packaged by using a packaged circuit board. The packaged circuit board is provided with a receiving hole. The MEMS chip and the ASIC chip are respectively attached to two surfaces of the packaged circuit board and cover receiving hole. The MEMS chip and the ASIC chip are connected with each other via the packaged circuit board, and are connected to an external circuit via the packaged circuit board, thereby facilitating a circuit interconnection between the package and an electronic component.

Abstract: A fingerprint chip packaging method and a fingerprint chip package are provided. During a process of packaging a fingerprint chip, the fingerprint chip is directly packaged and protected by a mold compound layer to form a thin package. With the fingerprint chip packaging method and the fingerprint chip package, the thickness of the package is greatly reduced, which facilitates miniaturization of the electronic device. Further, since the mold compound layer formed after curing of a mold compound material has a great mechanical strength, the mold compound layer can serve as a carrier substrate for mounting other electronic components of the electronic device, such that the integration of the electronic device is greatly improved, the space of the circuit board is saved, thereby facilitating the miniaturization of the electronic device.

Abstract: A chip packaging method and a chip package are provided. According to the chip packaging method and the chip package, to-be-packaged chips are located in a plastic packaging layer, and front surfaces of the to-be-packaged chips are flush with a first surface of the plastic packaging layer, and the plastic packaging material for manufacturing the plastic packaging layer has good plasticity before a curing process, so that the formed first surface and the second surface have good smoothness, thereby ensuring the reliability of the package.

Abstract: An optical fingerprint recognition chip package and a packaging method are provided. In the optical fingerprint recognition chip package, a cover plate is arranged on a front surface of an optical fingerprint recognition chip, the cover plate includes a substrate and a light shielding layer. The light shielding layer is arranged on a surface of the substrate facing away from the optical fingerprint recognition chip. The substrate is provided with multiple first through holes for exposing photosensitive pixels of the optical fingerprint recognition chip. The light shielding layer is provided with multiple second through holes in one-to-one correspondence with the first through holes. During fingerprint recognition, light reflected by a finger is split through the first through holes and the second through holes, such that crosstalk among different photosensitive pixels is reduced, and the accuracy of fingerprint recognition is improved.

Abstract: A packaging method and a package for an image sensing chip are provided. The packaging method includes: providing a wafer including a first surface and a second surface opposite to the first surface, where the wafer has multiple image sensing chips arranged in a grid, each of the image sensing chips has an image sensing region and contact pads arranged on a side of the first surface; forming an opening corresponding to each of the contact pads and cutting trenches on a side of the second surface of the wafer, where the contact pad is exposed through the opening; filling the cutting trenches with a first photosensitive ink; and applying a second photosensitive ink on the second surface of the wafer to cover the opening with the second photosensitive ink and form a hollow cavity in the opening.

Abstract: A package-on-package structure of an image sensing chip is provided, which includes: an image sensing chip package, a control chip package and a circuit board. The image sensing chip package and the control chip package are arranged on the same surface of the control chip package in parallel. The image sensing chip package includes a first substrate and an image sensing chip. The control chip package includes a second substrate and a control chip. A second surface of the first substrate is electrically connected to a first region of a first surface of the second substrate, and the circuit board is electrically connected to a second region of the first surface of the second substrate. A package-on-package method for a package-on-package structure is further provided.

Abstract: An image sensing chip package and an image sensing chip packaging method are provided. In the image sensing chip package, an image sensing chip is located in a through hole of a substrate, and a front surface of the image sensing chip is flush with a first surface of the substrate. In this way, in the image sensing chip package, a height of the image sensing chip is controlled with the first surface of the substrate as a reference. Since the first surface of the substrate does not change in the packaging process, almost no uncontrollable factor affects the height of the image sensing chip.

Abstract: A package for an iris recognition imaging module and a method for manufacturing a package for an iris recognition imaging module are provided. An image sensing chip is bonded with a substrate having a window, with an image sensing region of the image sensing chip being facing towards the window and covered by the window. The image sensing chip is electrically connected with a wiring line. The substrate is provided with an infrared light-emitting diode (LED), and a shielding member for preventing at least a part of infrared light emitted by the infrared LED from entering the image sensing region. With the shielding member, the amount of infrared light of the infrared LED entering the image sensing chip can be reduced while providing compensation light, thereby reducing interference to the iris imaging and improving the accuracy of the iris recognition.

Abstract: A packaging method and package structure for an image sensing chip are provided. The method includes: providing a wafer including a first surface and a second surface opposite to the first surface, where the wafer has multiple image sensing chips arranged in a grid, each having an image sensing region and contact pads arranged on a side of the first surface of the wafer; forming openings extending towards the first surface on the second surface of the wafer, to expose the contact pads; forming V-shaped cutting trenches extending towards the first surface on the second surface of the wafer; and applying a photosensitive ink on the second surface of the wafer, to completely fill the V-shaped cutting trenches, cover the openings, and form a hollow cavity between each of the openings and the photosensitive ink.

Abstract: A packaging method and a packaging structure are provided. The method includes: providing a first substrate and a second substrate, the second substrate having a fist surface and a second surface opposite to each other, a side surface of the first substrate being adhered to the first surface of the second substrate via an adhesive layer; forming a groove structure on the second surface of the second substrate; providing a base, the base having a first surface and a second surface opposite to each other, the first surface of the base including a sensing region and multiple bonding pads around the sensing region; and laminating the second surface of the second substrate with the first surface of the base to form a cavity between the groove structure and the base, such that the sensing region is located in the cavity.