Abstract: Disclosed is a method for manufacturing an LCP-based flexible copper-clad laminate, comprising: providing an LCP substrate and subjecting the LCP substrate to a Hall ion source pre-treatment; forming an ion-implanted layer in a certain depth range below the surface of the LCP substrate via ion implantation; performing plasma deposition to form a plasma deposition layer onto the ion-implanted layer; performing magnetron sputtering deposition to deposit copper ions onto the plasma deposition layer and form a magnetron sputtering deposition layer; and plating the magnetron sputtering deposition layer with a thickened copper layer to obtain the LCP-based flexible copper-clad laminate. Also disclosed is an LCP-based flexible copper-clad laminate, wherein a peeling strength between a copper foil and the LCP substrate of the LCP-based flexible copper-clad laminate is greater than or equal to 0.5 N/mm, a surface roughness between the two is smaller than or equal to 0.

Abstract: A neighboring user node of a user node is selected by using an attention model, to determine a selective adjacency matrix of a relation network based on the selected neighboring user node. Then, a neighboring node representation is propagated to a corresponding user node based on a selective adjacency matrix by using a graph neural network, to obtain a user aggregation representation. A tapping behavior between a user and an object is fitted based on a similarity between the user aggregation representation and an object representation, to construct a prediction loss based on a difference between the tapping behavior and an existing tapping behavior, and update the attention model. The trained attention model can select a more reliable neighboring user.

Abstract: Embodiments of this specification provide methods and apparatuses for generating a graph node relationship representation and methods and apparatuses for predicting a graph node service relationship. In an implementation, a method includes: determining node representations of a first graph node and a second graph node based on performing node representation propagation and node representation aggregation starting from the first graph node and the second graph node, and generating a node relationship representation between the first graph node and the second graph node based on the node representations.

Abstract: A whole-airspace satellite search method and device based on a phased array antenna are provided. The present disclosure combines electronic scanning implemented by the phased array antenna with mechanical scanning implemented by a mechanical actuator. As for low-orbit satellite communication, the present disclosure achieves rapid search and aiming through the phased array antenna, and solves the problem of limited electronic scanning angle of the phased array antenna through a servo system of the mechanical actuator. On the other hand, the present disclosure supports whole-airspace search and aiming of high, medium, and low-orbit satellites through the combination of the electronic scanning implemented by the phased array antenna and the mechanical scanning implemented by the mechanical actuator.

Abstract: A phase adjusting circuit, a delay locking circuit, and a memory are provided. The phase adjusting circuit includes a detection circuit, a comparison circuit, a counter, and an adjustment circuit that are connected in sequence. The detection circuit is configured to detect a phase difference between a first clock signal and a second clock signal to obtain a first detection signal and a second detection signal. The comparison circuit is configured to perform duty cycle comparison of the first detection signal and the second detection signal to obtain a counting indication signal. The counter is configured to count a number of pulses of a preset counting clock signal based on the counting indication signal to obtain a count value. The adjustment circuit is configured to perform phase adjustment of the second clock signal based on the count value, so that the phase difference is a preset value.

Abstract: Provided is a display panel. The display panel includes a display substrate, a diffusion sheet, a transflective film, and a fingerprint identification circuit, wherein the diffusion sheet is provided with at least one through hole, and an orthographic projection of the at least one through hole onto the display substrate is within the orthographic projection of the fingerprint identification circuit onto the display substrate.

Abstract: The present disclosure provides a wire and arc additive manufacturing (WAAM) method for a titanium alloy. The method includes the following steps: step 1: performing a WAAM process assisted by cooling and rolling; step 2: milling side and top surfaces of an additive part; step 3: performing, by friction stir processing (FSP) equipment, an FSP process on the additive part, and applying cooling and rolling to a side wall of the additive part through a cooling and rolling device during the FSP process; step 4: finish-milling the top surface of the additive part for a WAAM process in the next step; and step 5: repeating the above steps cyclically until final forming of the part is finished. This WAAM method completely breaks dendritic structures and refines grains in the WAAM process of the titanium alloy, thereby effectively repairing defects such as pores and cracks.

Abstract: The present disclosure provides a wire and arc additive manufacturing (WAAM) method for a magnesium alloy. The method includes the following steps: step 1: performing a WAAM process assisted by cooling and rolling; step 2: milling side and top surfaces of an additive part; step 3: performing, by friction stir processing (FSP) equipment, an FSP process on the additive part, and applying cooling and rolling to a side wall of the additive part through a cooling and rolling device during the FSP process; step 4: finish-milling the top surface of the additive part for a WAAM process in the next step; and step 5: repeating the above steps cyclically until final forming of the part is finished. The present disclosure completely breaks dendritic structures and refines grains in the WAAM process of the magnesium alloy, thereby effectively repairing defects such as pores and cracks.

Abstract: A multi-row ultrasonic imaging apparatus and an ultrasonic imaging instrument are disclosed. The multi-row ultrasonic imaging apparatus includes a housing, and a first ultrasonic transducer, a second ultrasonic transducer, and an adjustment mechanism that are installed in the housing. Ultrasonic waves emitted by the first ultrasonic transducer and the second ultrasonic transducer can intersect to form a confocal point. At least one of the first ultrasonic transducer and the second ultrasonic transducer is connected to the adjustment mechanism to move relative to the housing under the action of the adjustment mechanism, so as to adjust the position of the confocal point.

Abstract: A data sampling circuit includes a first signal path and a second signal path. The first signal path is arranged to receive a first signal, process and transmit the first signal. The first signal path has a first delay, and the first delay includes a first physical delay and a compensation delay. The second signal path is arranged to receive a second signal, receive processed first signal from the first signal path, and sample the second signal according to the processed first signal.

Abstract: A write leveling circuit applied to a memory includes a write signal generation unit and a sampling unit. The write signal generation unit is configured to receive a first clock signal and a first indication signal, and delay a first write signal according to the first clock signal, the first indication signal and a specified bit in the first indication signal, and output a second write signal. The sampling unit is connected to the write signal generation unit, and configured to receive a first data strobe signal and the second write signal, and output a second sampling signal according to received first Data Strobe Signal (DQS) and the second write signal.

Abstract: A write leveling circuit applied to a memory includes: a write signal generation circuit configured to perform delay processing on a first write signal according to a received first clock signal, and output a second write signal; a delay circuit configured to perform delay processing on a received first data strobe signal, and output a second data strobe signal; and a sampling circuit connected to both the delay circuit and the write signal generation circuit, and configured to output a first sampling signal according to the received second data strobe signal and the received second write signal. The sampling circuit is further configured to receive the first data strobe signal, and output a second sampling signal according to the first data strobe signal and the second write signal.

Abstract: The present application proposes a display panel and a display device, the display panel includes a liquid crystal display module, a reflective film and a fingerprint identification module. The liquid crystal display module is on a first side of the reflective film, and the fingerprint identification module is on a second side of the reflective film opposite to the first side. The fingerprint identification module includes an invisible light emitting unit and an invisible light sensor. The invisible light emitting unit is configured to emit invisible light in a direction towards the reflective film, and the invisible light sensor is configured to receive reflected invisible light. The reflective film is configured to transmit the invisible light and reflect visible light reaching the reflective film through the liquid crystal display module.

Abstract: Logo candidates for a specific ISO data can be identified from external resources based on the enriched merchant data. Low quality images of the logo candidates are filtered out with image analysis including entropy ratio evaluations of the logo candidates. Also, the logo candidates are processed with high quality filtering including classification of the logo candidates with a deep learning classifier for distinguishing logos from non-logos. A logo from the logo candidates is selected to associate with the ISO data packets. A display having the selected logo associated with a transaction of the ISO data packets can be generated for display to users.

Abstract: The present application relates to an LED bracket, a light-emitting unit and a light-emitting assembly. A substrate of the LED bracket comprises a substrate main body, and a supporting part extending from the substrate main body into a side wall of a bowl portion of the LED bracket, wherein the supporting part extends from one conductive area to the other conductive area in the side wall of the bowl portion of the LED bracket, and at least extends to a side wall area corresponding to an insulating area on the side wall that insulates and isolates the two conductive areas.

Abstract: Embodiments provide an impedance calibration circuit, including: a calibration circuit configured to receive a first calibration clock signal, to perform impedance calibration on a basis of the first calibration clock signal, and to output a first stop signal when the calibration is completed; a first detection circuit configured to detect calibration time of the impedance calibration circuit, and to output a second stop signal when the calibration time reaches a preset value; and a calibration control circuit configured to receive the first stop signal and the second stop signal and to output the first calibration clock signal. When the first stop signal or the second stop signal is received, the calibration control circuit stops outputting the first calibration clock signal.

Abstract: A dual reference voltage generator, an equalizer circuit, and a memory are provided. The dual reference voltage generator is configured to receive an original code, a first code and a second code, generate a first reference voltage according to the received original code and first code, and generate a second reference voltage according to the received original code and second code. The first reference voltage is different from the second reference voltage.

Abstract: A circuit and method for data transmission, and a storage apparatus are provided. A mode register decoding module is configured to generate a mode register unselected enable signal, a mode register read enable signal, or a mode register write enable signal according to received mode register address information, a mode register read control signal, or a mode register write control signal. A mode register read-write module is configured to: cache data on data line according to mode register write enable signal in write state, and output selected data and unselected data after setting the unselected data to zero according to the mode register read enable signal and the mode register unselected enable signal in a read state. The logic gate module is configured to calculate an OR value of the data outputted by each mode register read-write module in the read state and output a calculation result.

Abstract: A comparison circuit includes a reference adjustment module, a signal receiving module, and a control module. The reference adjustment module is configured to receive a first reference signal and output a second reference signal. The reference adjustment module is further configured to receive an adjustment signal, and unidirectionally adjust the equivalent coefficient within a preset value interval when the adjustment signal is received. The signal receiving module is configured to receive the second reference signal and an external signal. The control module is configured to: receive an enable signal and the comparison signal; and during a period of continuously receiving the enable signal, when the comparison signal jumps, terminate the output of the adjustment signal.

Abstract: A data sampling circuit includes a frequency dividing circuit, a sampling circuit and a selection circuit. The frequency dividing circuit is configured to receive a first data sampling signal, and perform frequency dividing processing on the first data sampling signal to obtain multiple second data sampling signals associated with respective phases; the sampling circuit is configured to receive the multiple second data sampling signals and a first data signal, and sample the first data signal according to the multiple second data sampling signals to obtain multiple second data signals associated with respective phases; and the selection circuit is configured to receive preamble information and mode register set (MRS) information, and select among the multiple second data sampling signals and the plurality of second data signals according to the preamble information and the MRS information to obtain a target data sampling signal and a target data signal respectively.