Abstract: A circuit and method for data transmission, and a storage apparatus are provided. A mode register decoding module is configured to generate a mode register unselected enable signal, a mode register read enable signal, or a mode register write enable signal according to received mode register address information, a mode register read control signal, or a mode register write control signal. A mode register read-write module is configured to: cache data on data line according to mode register write enable signal in write state, and output selected data and unselected data after setting the unselected data to zero according to the mode register read enable signal and the mode register unselected enable signal in a read state. The logic gate module is configured to calculate an OR value of the data outputted by each mode register read-write module in the read state and output a calculation result.

Abstract: A comparison circuit includes a reference adjustment module, a signal receiving module, and a control module. The reference adjustment module is configured to receive a first reference signal and output a second reference signal. The reference adjustment module is further configured to receive an adjustment signal, and unidirectionally adjust the equivalent coefficient within a preset value interval when the adjustment signal is received. The signal receiving module is configured to receive the second reference signal and an external signal. The control module is configured to: receive an enable signal and the comparison signal; and during a period of continuously receiving the enable signal, when the comparison signal jumps, terminate the output of the adjustment signal.

Abstract: A data sampling circuit includes a frequency dividing circuit, a sampling circuit and a selection circuit. The frequency dividing circuit is configured to receive a first data sampling signal, and perform frequency dividing processing on the first data sampling signal to obtain multiple second data sampling signals associated with respective phases; the sampling circuit is configured to receive the multiple second data sampling signals and a first data signal, and sample the first data signal according to the multiple second data sampling signals to obtain multiple second data signals associated with respective phases; and the selection circuit is configured to receive preamble information and mode register set (MRS) information, and select among the multiple second data sampling signals and the plurality of second data signals according to the preamble information and the MRS information to obtain a target data sampling signal and a target data signal respectively.

Abstract: A phase adjusting circuit, a delay locking circuit, and a memory are provided. The phase adjusting circuit includes a detection circuit, a comparison circuit, a counter, and an adjustment circuit that are connected in sequence. The detection circuit is configured to detect a phase difference between a first clock signal and a second clock signal to obtain a first detection signal and a second detection signal. The comparison circuit is configured to perform duty cycle comparison of the first detection signal and the second detection signal to obtain a counting indication signal. The counter is configured to count a number of pulses of a preset counting clock signal based on the counting indication signal to obtain a count value. The adjustment circuit is configured to perform phase adjustment of the second clock signal based on the count value, so that the phase difference is a preset value.

Abstract: A voltage control method. A train traveling speed can be acquired; a target transformation ratio corresponding to the train traveling speed is determined according to correspondences between train traveling speeds and transformation ratios, the transformation ratio being a ratio of an input voltage to an output voltage; an input voltage is then transformed according to the target transformation ratio to obtain an output voltage, the output voltage being used for driving a train to travel. The correspondences between train traveling speeds and transformation ratios are obtained according to correspondences between train traveling speeds and train traction forces at different transformation ratios. By means of the method, the most suitable transformation ratio can be provided according to a traveling speed of a maglev train, thereby increasing the traction force of the maglev train and improving running efficiency.

Abstract: Implementations of the present specification provide a training method for a graph neural network, and relate to performing multiple rounds of iterative updating on a graph neural network based on a user relational graph, where any round of the multiple rounds includes: processing the user relational graph by using a current graph neural network, to obtain multiple classification prediction vectors corresponding to multiple user nodes in the user relational graph; allocating a corresponding pseudo classification label to a first quantity of unlabeled nodes in the multiple user nodes based on the multiple classification prediction vectors; determining, for each of the first quantity of unlabeled nodes, an information gain generated by training the current graph neural network by using the unlabeled node; and updating a model parameter in the current graph neural network according to a classification prediction vector and a real classification label that are corresponding to each labeled node in the multiple us

Abstract: Embodiments of the present disclosure provide a control method, a semiconductor memory, and an electronic device. When the semiconductor memory is in a preset test mode, a first Model Register (MR) and a second MR related to a Data Pin (DQ) are allowed to directly define the impedance of a Data Mask Pin (DM). The DM does not need to add definition of an output driver state and a related control circuit for the preset test mode to ensure that the preset test mode is adapted to the DM. The impedance of the DM may be tested in the preset test mode to avoid circuit processing errors.

Abstract: An impedance control strategy for a Data Mask Pin (DM pin) in a preset test mode is provided, so that the impedance of the DM pin in the preset test mode may be defined. In addition, the relation between a control signal configured to control whether to enable the DM pin in a Double Data Rate 5 SDRAM (DDR5) and a control signal configured to control whether the DM pin is a test object in a Package Output Driver Test Mode (PODTM) is specified. The impedance of the DM pin may be tested in the preset test mode.

Abstract: A control method includes: decoding a third Operand (OP) in a third Mode Register (MR) and a fourth OP in a first MR; and in response to the semiconductor memory being in a preset test mode, controlling, in a case where the third OP meets a first decoding condition, the impedance of a Data Mask (DM) pin to be a first value; or controlling, in a case where the third OP meets a second decoding condition, the impedance of the DM pin to be a second value according to the fourth OP; wherein the third OP is configured to indicate whether the DM pin is a test object in the preset test mode, and the fourth OP is configured to indicate whether the DM pin is enabled.

Abstract: A system on chip, an access command routing method, and a terminal are disclosed. The system on chip includes an IP core and a bus. The IP core is configured to: obtain, based on an access address corresponding to an access command, an address range configuration identifier corresponding to the access address; and transmit the access command and the address range configuration identifier to the bus, where the address range configuration identifier is used by the bus to route the access command. The bus is configured to route the access command to a system cache or an external memory based on the address range configuration identifier.

Abstract: The present invention provides a method for discovering a Bluetooth device. The method includes: receiving, by a second Bluetooth device, a first broadcast frame of a first Bluetooth device; determining, by the second Bluetooth device, whether the first broadcast frame includes first indication information; and if the first broadcast frame includes the first indication information, sending, by the second Bluetooth device, at least one second broadcast frame within a preset time period after receiving the first broadcast frame, where the second broadcast frame includes second indication information, and the second indication information is used to instruct a Bluetooth device receiving the second broadcast frame to exchange information with the second Bluetooth device.

Abstract: A jet polishing device capable of stably forming a Gaussian removal function includes: an auxiliary mounting mechanism; a jet machining mechanism. The jet machining mechanism is connected with the auxiliary mounting mechanism, the jet machining mechanism includes a rotation driving assembly, a positioning assembly and a jet machining assembly, the positioning assembly includes a linear guide rail, a slide mass, a first laser and a second laser, the rotation driving assembly is connected with the linear guide rail, the slide mass is slidably connected to the linear guide rail, the first laser is fixedly arranged relative to the linear guide rail, the jet machining assembly includes a mounting bracket fixedly connected with the slide mass, a nozzle mounting body rotatably connected to the mounting bracket and a nozzle arranged on the nozzle mounting body, and the second laser is connected with the nozzle mounting body.

Abstract: A tundish, wherein a steel passing hole (43) is provided at a lower portion of a gas-curtain weir refractory body (42); an argon duct (46), a gas chamber (45) and a gas-permeable brick (44) are connected to form a gas-curtain generating device, and the gas-curtain generating device is installed at the lower portion of the gas-curtain weir refractory body (42); the gas-permeable brick (44) is provided in association with the position of the steel passing hole (43), and a length of the gas-permeable brick is designed larger than a width of the steel passing hole (43); and a gas-curtain weir plate (4) is provided in a tundish container, the gas-curtain weir refractory body (42) crosses the tundish container horizontally, and divides the tundish container into a first region and a second region.

Abstract: A flexible support includes a first mounting channel for mounting a flexible water pipe, a second mounting channel for mounting a flexible supporting and positioning mechanism, a first connecting end, a second connecting end, and a support body. The support body capable of being bent and deformed. The support body coupled between the first connecting end and the second connecting end. The second mounting channel is located on one side of the first mounting channel. The first mounting channel and the second mounting channel respectively penetrate through the first connecting end, the support body and the second connecting end in sequence.

Abstract: Provided are a display panel and a display device, relating to the field of display technologies. The display panel includes a display substrate, a diffusion sheet, a transflective film, and a fingerprint identification circuit. Light of a target wavelength emitted by the fingerprint identification circuit may be reflected by an obstacle, and the light of the target wavelength reflected by the obstacle may be irradiated to the fingerprint identification circuit through at least one through hole in the diffusion sheet. The fingerprint identification circuit performs fingerprint identification according to the received light of the target wavelength reflected by the obstacle. Since an orthographic projection of the fingerprint identification circuit onto the display substrate is within a display area of the display substrate, the fingerprint identification circuit can be prevented from occupying a non-display area of the display substrate.

Abstract: Embodiments of the present application disclose a content generation method and apparatus. The method includes: acquiring product description information; selecting, by using a deep neural network model component, a content phrase matched with the product description information, wherein the deep neural network model component is obtained by training according to a plurality of pieces of historical product description information and historical content of the historical product description information; and generating content corresponding to the product description information based on the selected content phrase.

Abstract: A circuit and method for data transmission, and a storage apparatus are provided. A mode register decoding module is configured to generate a mode register unselected enable signal, a mode register read enable signal, or a mode register write enable signal according to received mode register address information, a mode register read control signal, or a mode register write control signal. A mode register read-write module is configured to: cache data on data line according to mode register write enable signal in write state, and output selected data and unselected data after setting the unselected data to zero according to the mode register read enable signal and the mode register unselected enable signal in a read state. The logic gate module is configured to calculate an OR value of the data outputted by each mode register read-write module in the read state and output a calculation result.

Abstract: A data sampling circuit includes a frequency dividing circuit, a sampling circuit and a selection circuit. The frequency dividing circuit is configured to receive a first data sampling signal, and perform frequency dividing processing on the first data sampling signal to obtain multiple second data sampling signals associated with respective phases; the sampling circuit is configured to receive the multiple second data sampling signals and a first data signal, and sample the first data signal according to the multiple second data sampling signals to obtain multiple second data signals associated with respective phases; and the selection circuit is configured to receive preamble information and mode register set (MRS) information, and select among the multiple second data sampling signals and the plurality of second data signals according to the preamble information and the MRS information to obtain a target data sampling signal and a target data signal respectively.

Abstract: An information processing method and apparatus, a computer device, and a storage medium are disclosed. In the method, a request to perform a payment operation is received. A service page is displayed and an image of at least one part of a user is captured, in response to the request to perform the payment operation. Authentication of the user is performed based on the captured image of the at least one part of the user. While the authentication of the user is performed, a graphical representation of the at least one part of the user that is generated based on the captured image of the at least one part of the user is displayed. The graphical representation is unique to the user. The payment operation is performed when the user is authenticated based on the captured image of the at least one part of the user.

Abstract: An oscillation period detection circuit and method, and semiconductor memory are provided. The oscillation period detection circuit includes an oscillator module, a control module, and a counting module. The oscillator module includes a target oscillator, and is configured to receive an enable signal and control the target oscillator to output an oscillation clock signal according to the enable signal; the control module is configured to receive the enable signal and the oscillation clock signal, and perform valid time reforming processing according to the oscillation clock signal and the enable signal to determine a target time; the counting module is configured to receive the enable signal and the oscillation clock signal, and perform period counting processing according to the enable signal and the oscillation clock signal to determine a target period number. The oscillation period of the target oscillator is calculated according to the target time and the target period number.