Abstract: An emitter includes an electron supply and a tunneling layer disposed on the electron supply. A cathode layer is disposed on the tunneling layer. A conductive electrode has multiple layers of conductive material. The multiple layers include a protective layer disposed on the cathode layer. The conductive electrode has been etched to define an opening thereby exposing a portion of the cathode layer.

Abstract: An emitter has an electron supply and a porous cathode layer having nanohole openings. The emitter also has a tunneling layer disposed between the electron supply and the cathode layer.

Abstract: An emitter has an electron supply layer and a tunneling layer formed on the electron supply layer. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within in which the tunneling layer is formed. A cathode layer is formed on the tunneling layer. A conductive layer is partially disposed on the cathode layer and partially on the insulator layer if present. The conductive layer defines an opening to provide a surface for energy emissions of electrons and/or photons. Preferably but optionally, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: An emitter has an electron supply layer and a tunneling layer formed on the electron supply layer. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within in which the tunneling layer is formed. A cathode layer is formed on the tunneling layer. A conductive layer is partially disposed on the cathode layer and partially on the insulator layer if present. The conductive layer defines an opening to provide a surface for energy emissions of electrons and/or photons. Preferably but optionally, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: A method for creating an electron lens includes the steps of applying a polymer layer on an emitter surface of an electron emitter and then curing the polymer layer to reduce volatile content.

Abstract: An emitter has an electron supply layer and a tunneling layer formed on the electron supply layer. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within in which the tunneling layer is formed. A cathode layer is formed on the tunneling layer to provide a surface for energy emissions of electrons and/or photons. Preferably, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: Processes which utilize rapid thermal processing (RTP) are provided for inexpensively producing high efficiency silicon solar cells. The RTP processes preserve minority carrier bulk lifetime .tau. and permit selective adjustment of the depth of the diffused regions, including emitter and back surface field (bsf), within the silicon substrate. In a first RTP process, an RTP step is utilized to simultaneously diffuse phosphorus and aluminum into the front and back surfaces, respectively, of a silicon substrate. Moreover, an in situ controlled cooling procedure preserves the carrier bulk lifetime .tau. and permits selective adjustment of the depth of the diffused regions. In a second RTP process, both simultaneous diffusion of the phosphorus and aluminum as well as annealing of the front and back contacts are accomplished during the RTP step.

Abstract: Processes which utilize rapid thermal processing (RTP) are provided for inexpensively producing high efficiency silicon solar cells. The RTP processes preserve minority carrier bulk lifetime .tau. and permit selective adjustment of the depth of the diffused regions, including emitter and back surface field (bsf), within the silicon substrate. Silicon solar cell efficiencies of 16.9% have been achieved. In a first RTP process, an RTP step is utilized to simultaneously diffuse phosphorus and aluminum into the front and back surfaces, respectively, of a silicon substrate. Moreover, an in situ controlled cooling procedure preserves the carrier bulk lifetime .tau. and permits selective adjustment of the depth of the diffused regions. In a second RTP process, both simultaneous diffusion of the phosphorus and aluminum as well as annealing of the front and back contacts are accomplished during the RTP step.

Abstract: A new process has been developed to achieve a very low SiO.sub.x /Si interface state density D.sub.it, low recombination velocity S (<2 cm/s), and high effective carrier lifetime T.sub.eff (>5 ms) for oxides deposited on silicon substrates at low temperature. The technique involves direct plasma-enhanced chemical vapor deposition (PECVD), with appropriate growth conditions, followed by a photo-assisted rapid thermal annealing (RTA) process. Approximately 500-A-thick SiO.sub.x layers are deposited on Si by PECVD at 250.degree. C. with 0.02 W/cm.sup.-2 rf power, then covered with SiN or an evaporated thin aluminum layer, and subjected to a photo-assisted anneal in forming gas ambient at 350.degree. C., resulting in an interface state density D.sub.it in the range of about 1-4.times.10.sup.10 cm.sup.-2 eV.sup.-1, which sets a record for the lowest interface state density D.sub.it for PECVD oxides fabricated to date.

Abstract: A sequential plasma-enhanced chemical vapor deposition (PECVD) of SiN and SiO.sub.x produces a very effective double-layer antireflection coating. This antireflection coating is compared with the frequently used and highly efficient double-layer MgF.sub.2 /ZnS coating. It is shown that the double-layer SiO.sub.x /SiN coating improves the short-circuited current (J.sub.sc) by 47%, open-circuit voltage (V.sub.oc) by 3.7%, and efficiency (Eff) by 55% for silicon cells with oxide surface passivation. The counterpart MgF.sub.2 /ZnS coating gives smaller improvement in V.sub.oc and Eff. However, if silicon cells do not have the oxide passivation, the PECVD SiO.sub.x /SiN gives much greater improvement in the cell parameters, 57% in J.sub.sc, 8% in V.sub.oc, and 66% in efficiency, compared to the MgF.sub.2 /ZnS coating which improves J.sub.sc by 50%, V.sub.oc by 2%, and cell efficiency by 54%. This significant additional improvement results from the PECVD deposition-induced surface/defect passivation.