Patents by Inventor Zhizheng Liu
Zhizheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240080977Abstract: According to an example, a structure is generally described. The structure may include an inductor core having a plurality of surfaces; and at least one conductor integrated with at least one surface of the plurality of surfaces of the inductor core.Type: ApplicationFiled: May 8, 2023Publication date: March 7, 2024Applicant: Renesas Electronics America Inc.Inventors: Zhizheng LIU, Haiyu ZHANG, Sri Ganesh A THARUMALINGAM, Mark Alan KWOKA, Yonggoo EOM
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Patent number: 11894352Abstract: A power electronic module is provided that includes an electrical connection on opposing surfaces of an electronic component that allows a high current path from a top board to a bottom board through the body of the electronic component thus improving the power electronic module's electrical resistance and reducing the current load on the connector structure which is located between the first substrate and the second substrate. The power electronic module further includes a semiconductor component positioned on an external surface of the top board which allows for thermal contact of the semiconductor component with an external heat sink thus providing an efficient system thermal management via a reduced heat dissipation path. Additional heat dissipation can be obtained by disposing a metallic spacer on the semiconductor component of the power electronic module of the present disclosure.Type: GrantFiled: May 18, 2021Date of Patent: February 6, 2024Assignee: Renesas Electronics America Inc.Inventors: Sri Ganesh A Tharumalingam, Mark Kwoka, Viresh Piyush Patel, Peter Zhizheng Liu, Jeff Strang
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Publication number: 20220375909Abstract: A power electronic module is provided that includes an electrical connection on opposing surfaces of an electronic component that allows a high current path from a top board to a bottom board through the body of the electronic component thus improving the power electronic module's electrical resistance and reducing the current load on the connector structure which is located between the first substrate and the second substrate. The power electronic module further includes a semiconductor component positioned on an external surface of the top board which allows for thermal contact of the semiconductor component with an external heat sink thus providing an efficient system thermal management via a reduced heat dissipation path. Additional heat dissipation can be obtained by disposing a metallic spacer on the semiconductor component of the power electronic module of the present disclosure.Type: ApplicationFiled: May 18, 2021Publication date: November 24, 2022Applicant: Renesas Electronics America Inc.Inventors: Sri Ganesh A Tharumalingam, Mark Kwoka, Viresh Piyush Patel, Peter Zhizheng Liu, Jeff Strang
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Patent number: 9171936Abstract: One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.Type: GrantFiled: December 6, 2006Date of Patent: October 27, 2015Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Shankar Sinha, Yi He, Zhizheng Liu, Ming-Sang Kwan
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Patent number: 9153596Abstract: Semiconductor devices having reduced parasitic current and methods of malting the semiconductor devices are provided. Further provided are memory devices having reduced adjacent wordline disturb. The memory devices contain wordlines formed over a semiconductor substrate, wherein at least one wordline space is formed between the wordlines. Adjacent wordline disturb is reduced by implanting one or more of indium, boron, and a combination of boron and indium in the surface of the at least one wordline space.Type: GrantFiled: February 23, 2009Date of Patent: October 6, 2015Assignee: Cypress Semiconductor CorporationInventors: Gulzar A. Kathawala, Zhizheng Liu, Kuo Tung Chang, Lei Xue
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Patent number: 9142311Abstract: Selecting an array from among a plurality of arrays in a memory as a reference array. An exemplary method includes evaluating memory cells within the reference array to select a first reference cell associated with a first operation of the memory, and repeating the evaluating and the selecting to select a second reference cell from within the reference array, the second reference cell being associated with a second operation of the memory.Type: GrantFiled: June 13, 2013Date of Patent: September 22, 2015Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Zhizheng Liu, Cindy Sun, He Yi, Gulzar Kathawala
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Publication number: 20150103601Abstract: Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase. This sequential application of the single soft programming voltage pulse in the first phase may repeat a predetermined number of times or until a threshold is met. Once the predetermined number of times completes, or the threshold is met, soft programming proceeds to a second phase where soft programming remains with each word line until all memory cells along the word line passes soft programming verification.Type: ApplicationFiled: October 10, 2013Publication date: April 16, 2015Applicant: Spansion LLCInventors: Gulzar A. KATHAWALA, Mark W. RANDOLPH, Yi HE, Zhizheng LIU, Tio Wei NEO, Cindy SUN, Shivananda SHETTY, Phuog BANH, Richard FASTOW, Loi LA, Harry Hao KUO
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Patent number: 8995198Abstract: Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase. This sequential application of the single soft programming voltage pulse in the first phase may repeat a predetermined number of times or until a threshold is met. Once the predetermined number of times completes, or the threshold is met, soft programming proceeds to a second phase where soft programming remains with each word line until all memory cells along the word line passes soft programming verification.Type: GrantFiled: October 10, 2013Date of Patent: March 31, 2015Assignee: Spansion LLCInventors: Gulzar A. Kathawala, Mark W. Randolph, Yi He, Zhizheng Liu, Tio Wei Neo, Cindy Sun, Shivananda Shetty, Phuong Banh, Richard Fastow, Loi La, Harry Hao Kuo
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Publication number: 20140369141Abstract: Selecting an array from among a plurality of arrays in a memory as a reference array. An exemplary method includes evaluating memory cells within the reference array to select a first reference cell associated with a first operation of the memory, and repeating the evaluating and the selecting to select a second reference cell from within the reference array, the second reference cell being associated with a second operation of the memory.Type: ApplicationFiled: June 13, 2013Publication date: December 18, 2014Inventors: Zhizheng Liu, Cindy Sun, He Yi, Gulzar Kathawala
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Publication number: 20140233339Abstract: A non-volatile memory device comprising a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line; and at least an address decoder to provide a negative voltage to at least one non-accessed word line in said array when a programming or erasure voltage is provided along a shared bit line.Type: ApplicationFiled: February 18, 2013Publication date: August 21, 2014Applicant: SPANSION LLC.Inventors: Amichai GIVANT, Ilan BLOOM, Mark RANDOLPH, Zhizheng LIU
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Patent number: 8559255Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: GrantFiled: August 8, 2012Date of Patent: October 15, 2013Assignee: Spansion LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Patent number: 8404541Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.Type: GrantFiled: May 28, 2010Date of Patent: March 26, 2013Assignee: Spansion LLCInventors: Wei Zheng, Jean Yang, Mark Randolph, Ming Kwan, Yi He, Zhizheng Liu, Meng Ding
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Publication number: 20120294103Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: ApplicationFiled: August 8, 2012Publication date: November 22, 2012Applicant: SPANSION LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Patent number: 8264165Abstract: An apparatus and method for dimming a light emitting diode (LED) driver. The apparatus includes a triode alternating current (TRIAC) dimmer and an LED driver receiving an input voltage from an output of the TRIAC dimmer so that the state of the LED driver is controlled by the TRIAC dimmer. The LED driver includes an active damping circuit configured for damping, upon detecting a rising edge of a bridge rectified input voltage, resonance caused by the TRIAC dimmer and the LED driver for a fixed period of time.Type: GrantFiled: June 30, 2009Date of Patent: September 11, 2012Assignee: Linear Technology CorporationInventors: Wei Gu, Zhizheng Liu
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Patent number: 8264898Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: GrantFiled: June 9, 2011Date of Patent: September 11, 2012Assignee: Spansion LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Patent number: 8203178Abstract: A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.Type: GrantFiled: August 20, 2010Date of Patent: June 19, 2012Assignee: Spansion LLCInventors: Ashot Melik Martirosian, Zhizheng Liu, Mark Randolph
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Publication number: 20110235412Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: ApplicationFiled: June 9, 2011Publication date: September 29, 2011Applicant: Spansion LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Patent number: 7995386Abstract: Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.Type: GrantFiled: November 21, 2008Date of Patent: August 9, 2011Assignee: Spansion LLCInventors: Yuji Mizuguchi, Mark W. Randolph, Darlene Gay Hamilton, Yi He, Zhizheng Liu, Yanxia (Emma) Lin, Xianmin Yi, Gulzar Kathawala, Amol Ramesh Joshi, Kuo-Tung Chang, Edward Franklin Runnion, Sung-Chul Lee, Sung-Yong Chung, Yanxiang Liu, Yu Sun
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Patent number: 7986562Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.Type: GrantFiled: December 30, 2009Date of Patent: July 26, 2011Assignee: Spansion LLCInventors: Sung-Yong Chung, Zhizheng Liu, Yugi Mizuguchi, Xuguang Alan Wang, Yi He, Ming Kwan, Darlene Hamilton, Sung-Chul Lee, Guowei Wang, Nancy Leong
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Patent number: 7977218Abstract: Novel fabrication methods implement the use of dummy tiles to avoid the effects of in-line charging, ESD events, and such charge effects in the formation of a memory device region region. One method involves forming at least a portion of a memory core array upon a semiconductor substrate that involves forming STI structures in the substrate substantially surrounding a memory device region region within the array. An oxide layer is formed over the substrate in the memory device region region and over the STI's, wherein an inner section of the oxide layer formed over the memory device region region is thicker than an outer section of the oxide layer formed over the STI's. A first polysilicon layer is then formed over the inner and outer sections comprising one or more dummy tiles formed over one or more outer sections and electrically connected to at least one inner section.Type: GrantFiled: December 26, 2006Date of Patent: July 12, 2011Assignee: Spansion LLCInventors: Cinti Chen, Yi He, Wenmei Li, Zhizheng Liu, Ming-Sang Kwan, Yu Sun, Jean Yee-Mei Yang