Abstract: A system for programming a charge stored on a charge storage region of a dielectric charge trapping layer of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a positive source programming bias to a first bit line that is the source of the selected memory cell while applying a drain programming voltage to a second bit line that forms a drain junction with the channel region and while applying a positive voltage to a selected word line. The source voltage may be applied by coupling the source bit line to a voltage divider or by coupling the source bit line to a resistor which in turn is coupled to a ground. A negative programming bias may also be applied to the substrate and to unselected word lines.

Abstract: A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.

Abstract: The present invention is a method and system for erasing a nitride memory device. In one embodiment of the present invention, an isolated P-well is formed in a semiconductor substrate. A plurality of N-type impurity concentrations are formed in the isolated P-well and a nitride memory cell is fabricated between two of the N-type impurity concentrations. Finally, an electrical contact is coupled to the isolated P-well.

Abstract: An array of non-volatile memory cells is provided for storing a data pattern and reproducing the data pattern. The array comprises a semiconductor substrate moderately doped with a first type of impurity to enhance conductivity. A plurality of bit lines within the substrate define a plurality of vertical channel regions spaced there between. Each bit line comprises the substrate doped with a second type of impurity to enhance conductivity. Each channel comprises a moderately doped channel region portion adjacent to a first one of the bit lines and a slightly more heavily doped channel region portion adjacent to a second one of the bit lines. A plurality of parallel spaced apart semiconductor word lines are positioned over the substrate and separated from the substrate by an insulator film, a charge storage region, and a second insulator film.

Abstract: A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.

Abstract: A method of erasing a sector of flash memory cells wherein a first set of preset pre-erase voltages is applied to the sector of flash memory cells. After the first set of preset pre-erase voltages is applied it is determined if another set of preset pre-erase voltages is to be applied to the sector of flash memory cells. If another set of preset pre-erase voltages is applied and if another set of preset pre-erase set of pre-erase voltages is not to be applied, a standard erase routine is applied to the sector.

Abstract: A method for correcting overerasure in a multi-bit memory device. A sector of multi-bite memory cells in the device is erased and verified. After erase and verification, the overerased memory cells are soft programmed and verified to correct for overerasure. A soft programming pulse with a Vg to Vd ratio (Vg/Vd) greater than or equal to two is used.

Abstract: A memory circuit employed in a memory device is disclosed. According to one embodiment, the memory circuit comprises a first memory cell and a second memory cell. The first memory cell has a drain terminal connected to a bit line, which is connected to a sensing circuit. The first memory cell also has a control gate connected to a word line. The second memory cell also has a drain terminal connected to the bit line. The second memory cell has its control gate coupled to ground. The memory circuit supplies a source voltage greater than a ground voltage to a source terminal of the first memory cell and to a source terminal of the second memory cell such that the gate-to-source voltage of the second memory cell is less than the threshold voltage of the second memory cell.

Abstract: A resonant reset dual switch forward converter is disclosed. The resonant reset dual switch forward converter includes an input for accepting a DC voltage; a transformer having a primary winding and a secondary winding; a first and a second switch connected in series with the primary winding of the transformer for periodically connecting the input to the primary winding; a resonant capacitor for resetting the transformer during the OFF time of the first and second switches; and an auxiliary switch remaining OFF during the ON time of the first and second switches, and connecting the primary winding to the resonant capacitor during the OFF time of the first and second switches. The resonant reset dual switch forward converter provides a switching duty cycle greater than 50%, obtains a zero-voltage-switching condition for the first and second switches, and maintains the voltage stress of the f first and second switches around the input voltage.

Abstract: A resonant reset dual switch forward converter is disclosed. The resonant reset dual switch forward converter includes an input for accepting a DC voltage; a transformer having a primary winding and a secondary winding; a first and a second switch connected in series with the primary winding of the transformer for periodically connecting the input to the primary winding; a resonant capacitor for resetting the transformer during the OFF time of the first and second switches; and an auxiliary switch remaining OFF during the ON time of the first and second switches, and connecting the primary winding to the resonant capacitor during the OFF time of the first and second switches. The resonant reset dual switch forward converter provides a switching duty cycle greater than 50%, obtains a zero-voltage-switching condition for the first and second switches, and maintains the voltage stress of the first and second switches around the input voltage.