Patents by Inventor Zhong Hong
Zhong Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11848268Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: GrantFiled: July 16, 2021Date of Patent: December 19, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
-
Publication number: 20230386907Abstract: An electronic device includes a semiconductor die having a multilevel metallization structure including stacked levels with respective dielectric layers and metal lines, and a low leakage, low hydrogen diffusion barrier layer on one of the stacked levels. The diffusion barrier layer contacts a side of the dielectric layer and the metal line of the one of the stacked levels, and the diffusion barrier layer includes silicon nitride material having a first bond percentage ratio of ammonia to silicon nitride that is greater than a second bond percentage ratio of silicon hydride to silicon nitride.Type: ApplicationFiled: May 24, 2022Publication date: November 30, 2023Inventors: Qi-Zhong Hong, Joseph Jian Song, Gregory Boyd Shinn, Bhaskar Srinivasan
-
Publication number: 20230154915Abstract: An electronic device includes a first thin film resistor and a second thin film resistor above a dielectric layer that extends in a first plane of orthogonal first and second directions, the first resistor has three portions with the second portion extending between the first and third portions, and a recess etched into the top side of the second portion by a controlled etch process to increase the sheet resistance of the first resistor for dual thin film resistor integration.Type: ApplicationFiled: November 12, 2021Publication date: May 18, 2023Inventors: Bhaskar Srinivasan, Qi-Zhong Hong, Jarvis Benjamin Jacobs
-
Patent number: 11531130Abstract: There is disclosed in the present disclosure a seismic full horizon tracking method, a computer device and a computer-readable storage medium. The method includes: acquiring three-dimensional seismic data; extracting horizon extreme points from the three-dimensional seismic data to construct a sample space; equally dividing the sample space into a plurality of sub-spaces with overlapping portions, and performing a clustering process on the horizon extreme points in each sub-space to obtain horizon fragments corresponding to each horizon of the three-dimensional seismic data; establishing a topological consistency between the horizon fragments; and fusing the horizon fragments corresponding to each horizon of the three-dimensional seismic data based on the topological consistency, to obtain a full horizon tracking result of the three-dimensional seismic data.Type: GrantFiled: April 8, 2020Date of Patent: December 20, 2022Assignee: PETROCHINA COMPANY LIMITEDInventors: Mingjun Su, Zhong Hong, Qingyun Han, Tao Deng, Xiangli Cui, Feng Qian, Guangmin Hu, Yunze Xu
-
Patent number: 11424183Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.Type: GrantFiled: August 17, 2020Date of Patent: August 23, 2022Assignee: Texas Instruments IncorporatedInventors: Qi-Zhong Hong, Honglin Guo, Benjamin James Timmer, Gregory Boyd Shinn
-
Patent number: 11327194Abstract: The present disclosure discloses a method for identifying a boundary of a sedimentary facies, a computer device and a computer readable storage medium. The method comprises: acquiring a preliminary marked result of the sedimentary facies in a seismic attribute map; acquiring a color-based K-means classification result of the seismic attribute map by using a maximal between-cluster variance and a K-means clustering; acquiring a super-pixel classification result of the seismic attribute map according to a SLIC super-pixel segmentation; and performing a region growing fusion on the super-pixel classification result by taking the preliminary marked result and the K-means classification result as constraints, to determine an identification result of the boundary of the sedimentary facies in the seismic attribute map.Type: GrantFiled: August 7, 2020Date of Patent: May 10, 2022Assignee: PETROCHINA COMPANY LIMITEDInventors: Qilin Chen, Xingmiao Yao, Changkuan Ni, Bo Yan, Huaqing Liu, Guangmin Hu, Zhong Hong, Haichao Jiao
-
Publication number: 20210343642Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: ApplicationFiled: July 16, 2021Publication date: November 4, 2021Inventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
-
Patent number: 11101212Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: GrantFiled: May 28, 2019Date of Patent: August 24, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
-
Publication number: 20210041588Abstract: The present disclosure discloses a method for identifying a boundary of a sedimentary facies, a computer device and a computer readable storage medium. The method comprises: acquiring a preliminary marked result of the sedimentary facies in a seismic attribute map; acquiring a color-based K-means classification result of the seismic attribute map by using a maximal between-cluster variance and a K-means clustering; acquiring a super-pixel classification result of the seismic attribute map according to a SLIC super-pixel segmentation; and performing a region growing fusion on the super-pixel classification result by taking the preliminary marked result and the K-means classification result as constraints, to determine an identification result of the boundary of the sedimentary facies in the seismic attribute map.Type: ApplicationFiled: August 7, 2020Publication date: February 11, 2021Inventors: Qilin CHEN, Xingmiao YAO, Changkuan NI, Bo YAN, Huaqing LIU, Guangmin HU, Zhong HONG, Haichao JIAO
-
Publication number: 20200381358Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.Type: ApplicationFiled: August 17, 2020Publication date: December 3, 2020Inventors: Qi-Zhong HONG, Honglin GUO, Benjamin James Timmer, Gregory Boyd SHINN
-
Publication number: 20200326442Abstract: There is disclosed in the present disclosure a seismic full horizon tracking method, a computer device and a computer-readable storage medium. The method includes: acquiring three-dimensional seismic data; extracting horizon extreme points from the three-dimensional seismic data to construct a sample space; equally dividing the sample space into a plurality of sub-spaces with overlapping portions, and performing a clustering process on the horizon extreme points in each sub-space to obtain horizon fragments corresponding to each horizon of the three-dimensional seismic data; establishing a topological consistency between the horizon fragments; and fusing the horizon fragments corresponding to each horizon of the three-dimensional seismic data based on the topological consistency, to obtain a full horizon tracking result of the three-dimensional seismic data.Type: ApplicationFiled: April 8, 2020Publication date: October 15, 2020Inventors: Mingjun Su, Zhong Hong, Qingyun Han, Tao Deng, Xiangli Cui, Feng Qian, Guangmin Hu, Yunze Xu
-
Patent number: 10784193Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.Type: GrantFiled: July 27, 2018Date of Patent: September 22, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Qi-Zhong Hong, Honglin Guo, Benjamin James Timmer, Gregory Boyd Shinn
-
Publication number: 20200035598Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.Type: ApplicationFiled: July 27, 2018Publication date: January 30, 2020Inventors: QI-ZHONG HONG, HONGLIN GUO, BENJAMIN JAMES TIMMER, GREGORY BOYD SHINN
-
Patent number: 10439020Abstract: A method of fabricating integrated circuits (ICs) includes depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry including a plurality of interconnected transistors. A thin film resistor (TFR) layer including chromium (Cr) is deposited on the dielectric liner layer. The substrate is loaded into a hardmask layer deposition tool that includes a plasma source. The TFR layer is in-situ plasma pre-treated including flowing at least one inert gas and at least one oxidizing gas while in the hardmask layer deposition tool. A hardmask layer is deposited after the plasma pre-treating while remaining in the hardmask layer deposition tool. A pattern is formed on the hardmask layer, and the hardmask layer and TFR layer are etched stopping in the dielectric liner layer to form at least one resistor from the defined TFR layer.Type: GrantFiled: December 27, 2017Date of Patent: October 8, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abbas Ali, Dhishan Kande, Qi-Zhong Hong, Shih Chang Chang
-
Publication number: 20190295948Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: ApplicationFiled: May 28, 2019Publication date: September 26, 2019Inventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
-
Patent number: 10361095Abstract: A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a semiconductor device having a plurality of transistors. The metal interconnect layer is annealed at a maximum annealing temperature that is less than the first temperature. The metal interconnect layer is patterned after the annealing, thereby interconnecting the transistors.Type: GrantFiled: May 16, 2018Date of Patent: July 23, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abbas Ali, Dhishan Kande, Qi-Zhong Hong, Young-Joon Park, Kyle McPherson
-
Publication number: 20190221516Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: ApplicationFiled: January 16, 2018Publication date: July 18, 2019Inventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
-
Patent number: 10354951Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: GrantFiled: January 16, 2018Date of Patent: July 16, 2019Assignee: Texas Instruments IncorporatedInventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
-
Publication number: 20190198603Abstract: A method of fabricating integrated circuits (ICs) includes depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry including a plurality of interconnected transistors. A thin film resistor (TFR) layer including chromium (Cr) is deposited on the dielectric liner layer. The substrate is loaded into a hardmask layer deposition tool that includes a plasma source. The TFR layer is in-situ plasma pre-treated including flowing at least one inert gas and at least one oxidizing gas while in the hardmask layer deposition tool. A hardmask layer is deposited after the plasma pre-treating while remaining in the hardmask layer deposition tool. A pattern is formed on the hardmask layer, and the hardmask layer and TFR layer are etched stopping in the dielectric liner layer to form at least one resistor from the defined TFR layer.Type: ApplicationFiled: December 27, 2017Publication date: June 27, 2019Inventors: ABBAS ALI, DHISHAN KANDE, QI-ZHONG HONG, SHIH CHANG CHANG
-
Publication number: 20190108943Abstract: High voltage capacitors and methods of manufacturing the same are disclosed. An apparatus includes a first electrode of a capacitor above a semiconductor substrate. The first electrode is parallel to a plane perpendicular to the substrate. The apparatus further includes a second electrode spaced apart from the first electrode and parallel to the plane. The first electrode and the second electrode each including: (1) a first metal segment in a first metal layer, (2) a second metal segment in a second metal layer, and (3) a conductive via in an intermetal dielectric layer between the first and second metal layers interconnecting the first and second metal segments.Type: ApplicationFiled: October 11, 2017Publication date: April 11, 2019Inventors: Gang Liu, Qi-Zhong Hong