Abstract: Cavities such as vias and contacts formed in semiconductor devices are filled in a multi-stage process to provide low resistance electrical connections. A liner is first deposited into the cavity at a relatively low power and deposition rate to enhance "wetting" of a subsequently deposited fill material. The fill material is deposited at a comparatively greater power and deposition rate to close the mouth of the cavity, after which the fill material is extruded at high pressure into the cavity to substantially fill the cavity. Relatively low processing temperatures and high pressures are utilized to allow for the use of lower dielectric constant dielectrics, which are thermally unstable at conventional processing temperatures.

Abstract: An integrated circuit fabrication method for filling a high-aspect-ratio via with a metallization layer wherein there is provided a dielectric layer having a via therein. A wetting layer is deposited over the dielectric layer and within the via and the via sidewalls, the wetting layer being of a material which lowers the melting temperature of the metallization when combined with the metallization. The metallization layer is deposited over the wetting layer and the via but not completely filling the via with the metallization. The wetting agent with metallization thereon are heated to a temperature below the melting temperature of the metallization, the temperature being sufficient to cause the wetting layer to combine with the metallization, lower the melting temperature of the metallization to the temperature or below the heating temperature to cause the metallization to flow and fill the via.

Abstract: A process for producing conformal and stable TiN+Al films, which provides flexibility in selecting the chemical composition and layering. In this new process, porous TiCN is first deposited, and then Al is incorporated by exposing the porous film to CVD aluminum conditions at low temperatures.

Abstract: Method of fabricating a narrow linewidth transistor having a low sheet resistance. The transistor may be fabricated in a surface of a semiconductor layer (12). A gate body (14) may be formed separated from an outer surface (16) of the semiconductor layer (12) by a gate insulator (18). The gate body (14) may have an inner surface (20) proximate to the semiconductor layer (12) and an opposite outer surface (22). An insulator layer (30) may be deposited outwardly of the semiconductor layer (12) and the gate body (14). The insulator layer (30) may be anisotropically etched to form side walls (32) adjacent to the gate body (14). The anisotropic etch may cause a residual layer of contaminants (34) to form on the outer surface (16) of the semiconductor layer (12) and on the outer surface (22) of the gate body (14). A protective layer (50) may be deposited outwardly of the residual layer of contaminants (34). Dopants may be implanted into the semiconductor layer (12) proximate to the side walls (32).

Abstract: A method is provided for forming thin diffusion barriers in a semiconductor device (10). In one embodiment of the invention, a metal precursor gas is introduced to a surface of a dielectric layer. A predetermined amount of heat is then applied to the metal precursor gas and the dielectric layer. The heat causes the metal precursor gas to react with the dielectric layer, thereby forming a uniform, relatively thin diffusion barrier on the surface of the dielectric layer. In another embodiment of the invention, a metal precursor gas is introduced to a surface of a metal conductor. A predetermined amount of heat can then be applied to the metal precursor gas and the metal conductor, which creates a reaction between the gas and the conductor, and thereby produces a thin diffusion barrier on the surface of the metal conductor.

Abstract: A method to improve the texture of titanium and aluminum to reduce electromigration by controlling the deposition conditions and the texture of the substrates. Aluminum films can develop strong <111> texture, when titanium is used underneath aluminum. However, to prevent the interaction between aluminum and titanium, a layer of TiN or other barrier is necessary. Fortunately, TiN has a similar atom arrangement on the <111> plane as that of aluminum <111> and titanium <002>. Therefore, by controlling the orientation of titanium using a pre-sputter argon etch and low titanium deposition temperature, the texture of titanium can be transferred to TiN, and subsequently to aluminum.

Abstract: A method is provided for improving the texture of a metal interconnect (32) in a semiconductor device (10). A first layer of titanium (24), a layer of titanium nitride (26), a second layer of titanium (28), and a metal film (30) are sequentially formed over an oxide layer (12). The second titanium layer (28) is preferably out 10-20 nm thick. Because the metal film (30) is formed over the second titanium layer (28), any metal interconnect (32) that is formed as a part of the metal film (30) has a strong (111) crystalline orientation. Furthermore, because the second titanium layer (28) is relatively thin, the metal film (30) and metal interconnect (32) are not completely transformed into a metal compound having a high electrical resistance.

Abstract: A method of fabricating a transistor having an improved salicided gate is provided. The method may include forming a gate (14) that is separated from a substrate (12) by a gate insulator (16). A spacer (22) may be formed proximate the gate (14) such that the spacer (22) exposes a top region (28) and a side region (30) of the gate (14). The top region (28) and the side region (30) of the gate (14) may be irradiated at an angle (38) to form a post amorphous region (32) within the gate (14). A reactive layer (42) may be formed adjacent the post amorphous region (32). A salicidation region (44) may be then formed between the post amorphous region (32) and the reactive layer (42). The reactive layer (42) may be removed to expose the salicidation region (44).

Abstract: A method of removing an outer layer from an inner surface during semiconductor fabrication. A portion of the outer layer (50) may be anisotropically etched. A remaining portion of the outer layer (55) may then be wet etched without impairing the inner surface (12).

Abstract: Method of forming a salicide on a gate structure uses sidewall spacers which leave at least 30 percent of the gate sidewall exposed. After metal deposition, which has at least 50 percent step coverage, an anisotropic etch removes some or all of the metal on horizontal surfaces. Silicides formed from this metal layer are conformal, or even thicker on the sides of the gate than on horizontal structures. This achieves low sheet resistance on the gate, while remaining compatible with shallow junctions.

Abstract: A barrier/liner structure (10) and method. First, a porous nitride layer (12) is formed over a structure (18), for example, by metal-organic CVD (MOCVD). Then, the porous nitride layer (12) is exposed to a silicon- (or dopant-) containing ambient to obtain a silicon-(or dopant) rich surface layer (14). Finally, the silicon- (or dopant) rich surface layer (14) is nitrided to obtain a silicon-nitride (or dopant-nitride) enriched surface layer (16).

Abstract: Method of fabricating a narrow linewidth transistor having a low sheet resistance. The transistor may be fabricated in a surface of a semiconductor layer (12). A gate body (14) may be formed separated from an outer surface (16) of the semiconductor layer (12) by a gate insulator (18). The gate body (14) may have an inner surface (20) proximate to the semiconductor layer (12) and an opposite outer surface (22). An insulator layer (30) may be deposited outwardly of the semiconductor layer (12) and the gate body (14). The insulator layer (30) may be anisotropically etched to form side walls (32) adjacent to the gate body (14). The anisotropic etch may cause a residual layer of contaminants (34) to form on the outer surface (16) of the semiconductor layer (12) and on the outer surface (22) of the gate body (14). A protective layer (50) may be deposited outwardly of the residual layer of contaminants (34). Dopants may be implanted into the semiconductor layer (12) proximate to the side walls (32).

Abstract: A method is provided for forming sidewall diffusion barriers from a dielectric material. A trench or via is formed in a semiconductor device. A layer of dielectric material is deposited over the surfaces of the semiconductor device. The deposited layer of dielectric material is removed from all surfaces except the sidewall of the trench or via, thereby forming the dielectric diffusion barriers on the sidewall. Because dielectric materials have an amorphous structure which does not readily permit diffusion, impurities do not need to be added to the dielectric diffusion barriers. Furthermore, dielectric diffusion barriers produce a smaller RC time delay relative to metallic diffusion barriers having a comparable thickness.

Abstract: Methods are provided for the construction of metal-to-metal connections between non-adjacent layers in a structure, such as a semiconductor device. A first metal conductor layer is provided along a substrate. An anti-reflection cap is provided in overlying relation with said first conductor layer. At least a portion of the dielectric layer and the anti-reflection cap is removed to define a passage which extends from an upper surface of the dielectric layer to the first metal conductor. The passage is substantially filled with a fill metal, and a second metal conductor layer is applied over at least a portion of the dielectric layer and the substantially filled passage to electrically connect the first and second metal conductors. A diffusion liner can optionally be applied to the passage prior to application of the fill metal. The passage fill metal and second conductor layer can be integrally formed, and the fill metal and at least one of the conductor layers are formed from the same matrix metal.

Abstract: A device having a thin film and/or a solder ball formed on a substrate. The thin film and the solder ball each include a metal and a compound that includes an oxide, nitride, or carbide precipitate of an expandable element or a contractible element. The compound is distributed in the metal to control the tensile and compressive stresses and mechanical properties of the thin film and the solder ball.

Abstract: Methods are provided for the construction of metal-to-metal connections between non-adjacent layers in a structure, such as a semiconductor device. A first metal conductor layer is provided along a substrate. An anti-reflection cap is provided in overlying relation with said first conductor layer. At least a portion of the dielectric layer and the anti-reflection cap is removed to define a passage which extends from an upper surface of the dielectric layer to the first metal conductor. The passage is substantially filled with a fill metal, and a second metal conductor layer is applied over at least a portion of the dielectric layer and the substantially filled passage to electrically connect the first and second metal conductors. A diffusion liner can optionally be applied to the passage prior to application of the fill metal. The passage fill metal and second conductor layer can be integrally formed, and the fill metal and at least one of the conductor layers are formed from the same matrix metal.

Abstract: A method for forming thin films and controlling the tensile and compressive stresses and mechanical properties of the thin film. The method includes forming an alloy on a substrate having a solvent metal and a solute, then annealing the substrate and the alloy in one of an oxidizing, nitriding and carborizing ambient so that the ambient reacts with the solute to form respectively one of an oxide, nitride and carbide precipitates of the solute in the solvent. The solute is selected so that the precipitates formed may be used to control the mechanical properties of the solvent.

Abstract: A diffusion barrier trilayer 42 is comprised of a bottom layer 44, a seed layer 46 and a top layer 48. The diffusion barrier trilayer 42 prevents reaction of metallization layer 26 with the top layer 48 upon heat treatment, resulting in improved sheet resistance and device speed.

Abstract: A method and a device directed to the same, for stabilizing cobalt di-silicide/single crystal silicon, amorphous silicon, polycrystalline silicon, germanide/crystalline germanium, polycrystalline germanium structures or other semiconductor material structures so that high temperature processing steps (above 750.degree. C.) do not degrade the structural quality of the cobalt di-silicide/silicon structure. The steps of the method include forming a di-silicide or germanide by either reacting cobalt with the substrate material and/or the codeposition of the di-silicide or germanide on a substrate, adding a selective element, either platinum or nitrogen, into the cobalt and forming the di-silicide or germanide by a standard annealing treatment. Alternatively, the cobalt di-silicide or cobalt germanide can be formed after the formation of the di-silicide or germanide respectively. As a result, the upper limit of the annealing temperature at which the di-silicide or germanide will structurally degrade is increased.

Abstract: A method for minimizing reaction between metal conductors and other metals to minimize change in sheet resistance of the conductors upon heat treatment which includes providing a substrate. The substrate is preferably one of a dielectric, a metal or a semiconductor. A metallic diffusion barrier layer, preferably one of TiN, TiW or TiWN and preferably having a thickness of from about 10 nanometers to about 100 nanometers, is deposited on the substrate, preferably by one of sputtering, electron beam evaporation or chemical vapor deposition. The exposed surface of the metallic diffusion barrier layer is treated with a plasma, preferably an oxygen plasma, a nitrous oxide plasma or a plasma of an oxygen-containing species. An electrical conductor, preferably one of aluminum, aluminum-metal alloys, copper or copper-metal alloys and preferably having a thickness of from about 100 nanometers to about 1200 nanometers, is then deposited on the plasma-treated surface of the metallic diffusion barrier layer.