Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

Abstract: A display substrate and a display device are provided. The display substrate includes a display region including light emitting units; the light emitting units are arranged into light emitting unit rows, and the light emitting units in one of the light emitting unit rows are arranged along a first direction; the light emitting units include first light emitting units. In at least part of the display region: distances, in the first direction, between a light emitting region of one first light emitting unit and light emitting regions of two of the first light emitting units adjacent to the one first light emitting units are different, and/or distances, in a second direction, between a light emitting region of one first light emitting units and the light emitting regions of two of the first light emitting units adjacent to the one first light emitting units are different.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: A method of making an integrated circuit includes steps of selecting a first cell and a second cell for an integrated circuit layout from a cell library in an electronic design automation (EDA) system, the first and second cells each having a cell active area, a cell gate electrode, at least one fin of a first set of fins, and a cell border region, each cell also having the active area at an exposed side, and placing the first exposed side against the second exposed side at a cell border. The method also includes operations of aligning at least one fin of the first set of fins with at least one fin of the second set of fins across a cell border.

Abstract: Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.

Abstract: A method includes creating a layout design of the integrated circuit after determining a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor. Creating the layout design includes forming first-type active zone patterns, forming second-type active zone patterns, generating a gate-strip pattern, and positioning the gate-strip pattern over the first-type active zone patterns and the second-type active zone patterns. Creating the layout design also includes determining whether to generate one or more poly cut patterns that intersect the gate-strip, based on the difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.

Abstract: An Organic Light-Emitting Diode display substrate and a preparation method thereof. The Organic Light-Emitting Diode display substrate includes: a first flexible organic layer; a first inorganic layer on the first flexible organic layer; a second flexible organic layer on the first inorganic layer; a pixel driving circuit layer on the second flexible organic layer; a light-emitting element layer on the pixel driving circuit layer, and a thickness of the first flexible organic layer is 5 ?m-20 ?m, a thickness of the first inorganic layer is 0.4 ?m-0.5 ?m, and a thickness of the second flexible organic layer is 5 ?m-20 ?m.

Abstract: A display substrate motherboard and a preparation method thereof, a display substrate and a preparation method thereof are disclosed. The display substrate motherboard includes a base substrate, a first flexible organic layer, a first inorganic layer, a second flexible organic layer and a pixel driving circuit layer. The pixel driving circuit layer includes a plurality of pixel driving circuit portions respectively used for a plurality of display substrates, and the plurality of pixel driving circuit portions are insulated from each other. An orthogonal projection of the second flexible organic layer on the base substrate is located inside an orthogonal projection of the first inorganic layer on the base substrate. An orthogonal projection of each of the pixel driving circuit portions on the base substrate is located inside the orthogonal projection of the second flexible organic layer on the base substrate.

Abstract: A display substrate motherboard and a preparation method thereof, a display substrate and a preparation method thereof are disclosed. The display substrate motherboard includes a base substrate, a first flexible organic layer, a first inorganic layer, a second flexible organic layer and a pixel driving circuit layer. The pixel driving circuit layer includes a plurality of pixel driving circuit portions respectively used for a plurality of display substrates, and the plurality of pixel driving circuit portions are insulated from each other. An orthogonal projection of the second flexible organic layer on the base substrate is located inside an orthogonal projection of the first inorganic layer on the base substrate. An orthogonal projection of each of the pixel driving circuit portions on the base substrate is located inside the orthogonal projection of the second flexible organic layer on the base substrate.

Abstract: A display panel, a manufacturing method thereof and a display device. The display panel includes a first region and a second region. The second region includes a driving circuitry layer and a first light-emitting unit located on a base substrate, the first region includes a plurality of second light-emitting units located on the base substrate, the second light-emitting unit is electrically coupled to the driving circuitry layer through a transparent conductive layer, the transparent conductive layer includes at least two conductive sub-layers laminated one on another and insulated from each other, each conductive sub-layer includes at least one transparent conductive line, and each transparent conductive line is coupled to a corresponding second light-emitting unit.

Abstract: A display panel, a manufacturing method thereof and a display device are provided. The display panel includes a base substrate, the base substrate includes a display region and a peripheral region surrounding the display region, the base substrate includes a first substrate layer, a third substrate layer and a second substrate layer which are sequentially stacked, a material of the second substrate layer includes amorphous silicon. The display region includes a transparent display region, the transparent display region includes a pixel region and a light transmission region, and a thickness of the second substrate layer located in the light transmission region is less than a thickness of at least part of the second substrate layer located outside the transparent display region.

Abstract: An action evaluation model building apparatus and an action evaluation model building method thereof are provided. The action evaluation model building apparatus stores a plurality of raw data sets and a plurality of standard action labels corresponding thereto. Based on machine learning algorithms, the action evaluation model building apparatus computes the raw data sets and performs a supervised learning to build a feature vector creation model and a classifier model. The action evaluation model building apparatus determines a representation action feature vector of each standard action label by randomly generating a plurality of action feature vectors and inputting them into the classifier model. The action evaluation model building apparatus builds an action evaluation model based on the feature vector creation model, the classifier model and the representation action feature vectors.

Abstract: A display panel, a manufacturing method thereof and a display device. The display panel includes a first region and a second region. The second region includes a driving circuitry layer and a first light-emitting unit located on a base substrate, the first region includes a plurality of second light-emitting units located on the base substrate, the second light-emitting unit is electrically coupled to the driving circuitry layer through a transparent conductive layer, the transparent conductive layer includes at least two conductive sub-layers laminated one on another and insulated from each other, each conductive sub-layer includes at least one transparent conductive line, and each transparent conductive line is coupled to a corresponding second light-emitting unit.

Abstract: This disclosure provides a deaeration apparatus comprising: a closable deaeration cavity configured to accommodate a liquid to be deaerated; a heating member configured to heat the deaeration cavity; a temperature detection member configured to detect a temperature inside the deaeration cavity; and a controller configured to receive the temperature detected by the temperature detection member and control the heating member based on the temperature. When using in deaeration of a liquid, the deaeration apparatus of the disclosure can shorten the deaeration time and improve the deaeration efficiency of the liquid.

Abstract: A curing apparatus and a curing method are provided. The curing apparatus comprises: a chamber, configured for accommodating a substrate provided with a polyimide adhesive; an air extracting unit, configured for evacuating the chamber; and a heating unit, configured for performing a first heating on the substrate in the case that a first predetermined pressure is reached in the chamber during a evacuating process of the air extracting unit so as to remove organic gases from the polyimide adhesive, and performing a second heating on the substrate after the first heating so as to cure the polyimide adhesive.

Abstract: An action evaluation model building apparatus and an action evaluation model building method thereof are provided. The action evaluation model building apparatus stores a plurality of raw data sets and a plurality of standard action labels corresponding thereto. Based on machine learning algorithms, the action evaluation model building apparatus computes the raw data sets and performs a supervised learning to build a feature vector creation model and a classifier model. The action evaluation model building apparatus determines a representation action feature vector of each standard action label by randomly generating a plurality of action feature vectors and inputting them into the classifier model. The action evaluation model building apparatus builds an action evaluation model based on the feature vector creation model, the classifier model and the representation action feature vectors.

Abstract: This disclosure provides a deaeration apparatus comprising: a closable deaeration cavity configured to accommodate a liquid to be deaerated; a heating member configured to heat the deaeration cavity; a temperature detection member configured to detect a temperature inside the deaeration cavity; and a controller configured to receive the temperature detected by the temperature detection member and control the heating member based on the temperature. When using in deaeration of a liquid, the deaeration apparatus of the disclosure can shorten the deaeration time and improve the deaeration efficiency of the liquid.

Abstract: A parking space status sensing system is used for detecting a state of a parking space. A parking space status sensing system includes a first antenna array transmitting a first signal, a second antenna array receiving a second signal feedback reflected from an object, a radio-frequency transceiver receiving the second signal and performing down-conversion and demodulation on the second signal with receiving a local signal modulated from a triangularly modulated signal by the radio-frequency transceiver, to generate a first beat frequency signal. An analog-distance-signal-integral information and an analog-speed-signal-integral information of the object are obtained from the first beat frequency signal by related analog signal processes.

Abstract: A method for fabricating an array substrate, an array substrate and a display device are provided. The method for fabricating the array substrate includes: forming a spacer layer on the array substrate, the spacer layer is disposed under a planarized layer and corresponds to a location of a via hole in the planarized layer, wherein the planarized layer is formed of a hot melt material.

Abstract: An apparatus and method for correcting the ionospheric distortion of an SAR (Synthetic Aperture Radar) interferogram are disclosed herein. The apparatus includes a multiple aperture SAR interferometry (MAI) interferogram generation unit, a transformed MAI interferogram generation unit, an ionospheric distortion interferogram generation unit, and a corrected SAR interferogram acquisition unit. The multiple aperture SAR interferometry (MAI) interferogram generation unit generates a multiple aperture SAR interferometry (MAI) interferogram using an SAR interferogram. The transformed MAI interferogram generation unit generates a transformed MAI interferogram representative of the azimuth direction derivatives of ionospheric distortion phases using the phases of the MAI interferogram. The ionospheric distortion interferogram generation unit generates an ionospheric distortion interferogram using the transformed MAI interferogram.