Abstract: The present disclosure relates to a liquid-cooling radiating pipe and a vacuum interrupter with a built-in liquid-cooling radiating pipe, belonging to the field of vacuum circuit breakers. Based on an original structure of an vacuum interrupter, a liquid-cooling radiating pipe of a Tesla valve structure is arranged in a conductive rod of the vacuum interrupter with the built-in liquid-cooling radiating pipe, and liquid metal is used as a circulating coolant in the liquid-cooling radiating pipe, and by using the self-circulating flow of the liquid metal in the pipeline, the capacity of the conductive rod to dissipate heat to the outside is significantly increased, and the problem of excessive internal temperature rise of a vacuum circuit breaker is effectively solved.

Abstract: The disclosure relates to the technical field of projection auto-focusing, and embodiments particularly disclose a projection focusing method, a projection focusing apparatus, a projector, and a readable storage medium. According to the projection focusing method provided by this application, an initial position of a focused motor is roughly determined based on a current projection distance, a focusing direction is determined according to the current projection distance and a projection distance corresponding to the current motor position, a position of a clearest projection picture can be found by traversing a few motor positions, and the speed and precision of projection focusing are greatly increased.

Abstract: The present disclosure relates to the technical field of compensation for projection thermal defocusing, and the embodiments specifically disclose a bidirectional compensation method and apparatus for projection thermal defocusing, and a readable storage medium.

Abstract: The disclosure relates to the technical field of projection auto-focusing, and embodiments particularly disclose a projection focusing method, a projection focusing apparatus, a projector, and a readable storage medium. According to the projection focusing method provided by this application, an initial position of a focused motor is roughly determined based on a current projection distance, a focusing direction is determined according to the current projection distance and a projection distance corresponding to the current motor position, a position of a clearest projection picture can be found by traversing a few motor positions, and the speed and precision of projection focusing are greatly increased.

Abstract: A system may include determination of a spatial power map associated with an integrated circuit based on an architecture of the circuit, generation of a spatial thermal map associated with the integrated circuit based on the spatial power map, and determination of a spatial leakage power map based on the spatial thermal map. In some aspects, a system includes determination of a temperature of an integrated circuit, comparison of the temperature with a thermal divergence temperature, determination that the temperature of the integrated circuit is primarily due to leakage power, and disabling of power to the integrated circuit.

Abstract: A method and apparatus for improving snooping performance is disclosed. In one embodiment, one or more content addressable matches are used to determine where and when an address conflict occurs. Depending upon the timing, a read request or a snoop request may be set for retry. In another embodiment, an age order matrix may be used to determine when several core snoop requests may be issued during a same time period, so that the snoops may be processed during this time period.

Abstract: Preventing request conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to manage request conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches shared amongst a set of cores or processors or agents.

Abstract: A method and apparatus for improving snooping performance is disclosed. In one embodiment, one or more content addressable matches are used to determine where and when an address conflict occurs. Depending upon the timing, a read request or a snoop request may be set for retry. In another embodiment, an age order matrix may be used to determine when several core snoop requests may be issued during a same time period, so that the snoops may be processed during this time period.

Abstract: Preventing request conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to manage request conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches shared amongst a set of cores or processors or agents.

Abstract: Systems and methods to implement a multi-level memory system having a volatile memory and a non-volatile memory are implemented. A home agent may control memory access to both a volatile main memory and a non-volatile second level memory. The second level memory may be inclusive of the main memory. In an embodiment, the home agent may be configured to manage the memory system in a low power state. In a low power state, the volatile memory may be shut down and the non-volatile memory utilized as the only local memory. In an embodiment, the home agent may be configured to manage error recovery for the main memory by recovering the data saved locally in the second level memory. In an embodiment, multiple cores may access the second level memory.

Abstract: A mechanism is described for facilitating customization of multipurpose interconnect agents at computing devices according to one embodiment of the invention. A method of embodiments of the invention includes enhancing a multipurpose interconnect agent by associating a customization block to the multipurpose interconnect agent at a computing system. Enhancing may include customization of one or more functionalities of the multipurpose interconnect agent. The method may further include customizing, via the customization block, the one or more functionalities of the enhanced multipurpose interconnect agent, wherein customizing includes enabling integration of two or more processor interconnects carrying data packets.

Abstract: A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response, to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance.

Abstract: Methods, systems, and apparatus for implementing raw memory transactions. An SoC is configured with a plurality of nodes coupled together forming a ring interconnect. Processing cores and memory cache components are operatively coupled to and co-located at respective nodes. The memory cache components include a plurality of last level caches (LLC's) operating as a distributed LLC and a plurality of home agents and caching agents employed for supporting coherent memory transactions. Route-back tables are used to encode memory transactions requests with embedded routing data that is implemented by agents that facilitate data transfers between link interface nodes and memory controllers. Accordingly, memory request data corresponding to raw memory transactions may be routed back to requesting entities using headerless packets.

Abstract: A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response, to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance.

Abstract: A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance.

Abstract: A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance.

Abstract: A system, method, and computer program product for retaining coherent cache contents during deep power-down operations, and reducing the low-power state entry and exit overhead to improve processor energy efficiency and performance. The embodiments flush or clean the Modified-state lines from the cache before entering a deep low-power state, and then implement a deferred snoop strategy while in the powered-down state. Upon existing the powered-down state, the embodiments process the deferred snoops. A small additional cache and a snoop filter (or other cache-tracking structure) may be used along with additional logic to retain cache contents coherently through deep power-down operations, which may span multiple low-power states.

Abstract: Systems and methods to implement a multi-level memory system having a volatile memory and a non-volatile memory are implemented. A home agent may control memory access to both a volatile main memory and a non-volatile second level memory. The second level memory may be inclusive of the main memory. In an embodiment, the home agent may be configured to manage the memory system in a low power state. In a low power state, the volatile memory may be shut down and the non-volatile memory utilized as the only local memory. In an embodiment, the home agent may be configured to manage error recovery for the main memory by recovering the data saved locally in the second level memory. In an embodiment, multiple cores may access the second level memory.

Abstract: A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response, to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance.

Abstract: A mechanism is described for facilitating customization of multipurpose interconnect agents at computing devices according to one embodiment of the invention. A method of embodiments of the invention includes enhancing a multipurpose interconnect agent by associating a customization block to the multipurpose interconnect agent at a computing system. Enhancing may include customization of one or more functionalities of the multipurpose interconnect agent. The method may further include customizing, via the customization block, the one or more functionalities of the enhanced multipurpose interconnect agent, wherein customizing includes enabling integration of two or more processor interconnects carrying data packets.