Abstract: Methods, systems, and apparatus for implementing raw memory transactions. An SoC is configured with a plurality of nodes coupled together forming a ring interconnect. Processing cores and memory cache components are operatively coupled to and co-located at respective nodes. The memory cache components include a plurality of last level caches (LLC's) operating as a distributed LLC and a plurality of home agents and caching agents employed for supporting coherent memory transactions. Route-back tables are used to encode memory transactions requests with embedded routing data that is implemented by agents that facilitate data transfers between link interface nodes and memory controllers. Accordingly, memory request data corresponding to raw memory transactions may be routed back to requesting entities using headerless packets.

Abstract: A method and apparatus for cache coherency sequencing implementation and an adaptive LLC access priority control is disclosed. One embodiment provides mechanisms to resolve last level cache access priority among multiple internal CMP cores, internal snoops and external snoops. Another embodiment provides mechanisms for implementing cache coherency in multi-core CMP system.

Abstract: A system may include determination of a spatial power map associated with an integrated circuit based on an architecture of the circuit, generation of a spatial thermal map associated with the integrated circuit based on the spatial power map, and determination of a spatial leakage power map based on the spatial thermal map. In some aspects, a system includes determination of a temperature of an integrated circuit, comparison of the temperature with a thermal divergence temperature, determination that the temperature of the integrated circuit is primarily due to leakage power, and disabling of power to the integrated circuit.

Abstract: In an embodiment, the method provides receiving a memory access request for a demanded cache line from a processor of a plurality of processors; accessing coherency information associated with the demanded cache line from a memory unit by bringing in from a memory page in which the demanded cache line is stored, the memory page also including a directory line having coherency information corresponding to the demanded cache line; reading data associated with the demanded cache line in accordance with the coherency information; and returning the data to the processor.

Abstract: A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance.

Abstract: A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance.

Abstract: In an embodiment, the method provides receiving a memory access request for a demanded cache line from a processor of a plurality of processors; accessing coherency information associated with the demanded cache line from a memory unit by bringing in from a memory page in which the demanded cache line is stored, the memory page also including a directory line having coherency information corresponding to the demanded cache line; reading data associated with the demanded cache line in accordance with the coherency information; and returning the data to the processor.

Abstract: A system may include determination of a spatial power map associated with an integrated circuit based on an architecture of the circuit, generation of a spatial thermal map associated with the integrated circuit based on the spatial power map, and determination of a spatial leakage power map based on the spatial thermal map. In some aspects, a system includes determination of a temperature of an integrated circuit, comparison of the temperature with a thermal divergence temperature, determination that the temperature of the integrated circuit is primarily due to leakage power, and disabling of power to the integrated circuit.

Abstract: A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance.

Abstract: The present invention presents an efficient way to implement global ordering between a system interconnect and internal core interfaces in a MCMP system. In particular, snooping transactions on the system interconnect, processor requests, and processor request completions may trigger corresponding snooping transactions and request completions to the cores. The order in which the transactions are observed on the system interconnect may impose the order in which the transaction triggered to the core are generated. Since this ordering is between multiple interfaces this is referred to as global ordering.

Abstract: Methods and apparatus to adjust leakage power of a cache are described. In one embodiment, leakage power of a cache is adjusted based on the measured leakage power and a target leakage power value.

Abstract: A method and apparatus for adaptive multiple line prefetching. In one embodiment, the method includes the identification of a prefetch depth. As described herein, a prefetch depth may refer to a number of memory lines to be prefetched to temporary (cache) memory. Once the prefetch depth is identified, prefetching is performed according to the identified prefetch depth. During the prefetching, the prefetching is adjusted as changes in the prefetch depth are detected. Accordingly, the dynamic adaptive multi-line prefetching mechanism described herein promotes higher system performance by the use of a more efficient prefetching mechanism.

Abstract: A method and apparatus for improving snooping performance is disclosed. One embodiment provides mechanisms for processing multi-core evictions in a multi-core inclusive shared cache processor. By using parallel eviction state machine, the latency of eviction processing is minimized. Another embodiment provides mechanisms for processing multi-core evictions in a multi-core inclusive shared cache processor in the presence of external conflicts.

Abstract: A method and apparatus for cache coherency sequencing implementation and an adaptive LLC access priority control is disclosed. One embodiment provides mechanisms to resolve last level cache access priority among multiple internal CMP cores, internal snoops and external snoops. Another embodiment provides mechanisms for implementing cache coherency in multi-core CMP system.

Abstract: A processor having asymmetric secondary processing resources. One disclosed embodiment includes a first execution resource to perform a first function and a second execution resource that also performs the second function, although the second processing resource is asymmetric to the first resource in that it has a lower throughput than the first processing resource. Switching logic switches execution from the first processing resource to the second processing resource in a reduced power consumption mode.

Abstract: A method and apparatus for improving snooping performance is disclosed. In one embodiment, one or more content addressable matches are used to determine where and when an address conflict occurs. Depending upon the timing, a read request or a snoop request may be set for retry. In another embodiment, an age order matrix may be used to determine when several core snoop requests may be issued during a same time period, so that the snoops may be processed during this time period.

Abstract: A processor having asymmetric secondary processing resources. One disclosed embodiment includes a first execution resource to perform a first function and a second execution resource that also performs the second function, although the second processing resource is asymmetric to the first resource in that it has a lower throughput than the first processing resource. Switching logic switches execution from the first processing resource to the second processing resource in a reduced power consumption mode.

Abstract: The present invention presents an efficient way to implement global ordering between a system interconnect and internal core interfaces in a MCMP system. In particular, snooping transactions on the system interconnect, processor requests, and processor request completions may trigger corresponding snooping transactions and request completions to the cores. The order in which the transactions are observed on the system interconnect may impose the order in which the transaction triggered to the core are generated. Since this ordering is between multiple interfaces this is referred to as global ordering.

Abstract: A process for growing by chemical vapor deposition a heteroepitaxial single crystal diamond is disclosed. The process provides a substrate which enables the growth of single crystal diamond which is vapor coated on an iridium film. An intermediate process for producing a composite composition with diamond nuclei is also described. Further described are composite compositions of metal oxide, iridium and single crystal diamond films or diamond nuclei. Single crystal diamond is useful in a variety of electronics and acoustics fields.

Abstract: A method and apparatus for a microprocessor with a cache that has the advantages given by a victim cache without physically having a victim cache is disclosed. In one embodiment, a victim flag may be associated with each way in a set. At eviction time, the way whose victim flag is true may be evicted. However, the victim flag may be reset to false if a superceding request arrives for the cache line in that way. Another cache line in another way may then have its victim flag made true.