Abstract: In a general aspect, a method can include forming well region of one conductivity type in a semiconductor region of another conductivity type An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The method can further include forming at least one dielectric region in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.

Abstract: In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.

Abstract: A process of forming an electronic device can form an accumulation channel or an integrated diode by selective doping parts of a workpiece. In an embodiment, a doped region can be formed by implanting a sidewall of a body region. In another embodiment, a doped region can correspond to a remaining portion of a semiconductor layer after forming another doped region by implanting into a contact opening. The accumulation channel or the integrated diode can lower the barrier for a body diode turn-on. Reduced stored charge and QRR may be achieved, leading to lower switching losses.

Abstract: In one general aspect, an apparatus can include a substrate having a semiconductor region, and a trench defined in the semiconductor region and having a sidewall. The apparatus can include a shield electrode disposed in the trench and insulated from the sidewall of the trench by a shield dielectric, the shield dielectric having a low-k dielectric portion and a high-k dielectric portion. The apparatus can include a gate electrode disposed in the trench and at least partially surrounded by a gate dielectric, and an inter-electrode dielectric disposed between the shield electrode and the gate electrode.

Abstract: A device includes a mesa disposed between a pair of vertical trenches in a semiconductor substrate. A gate electrode is disposed in each of the pair of vertical trenches, and a shield electrode is disposed below each of the gate electrodes in the pair of vertical trenches. The device further includes a bridge connection trench traversing the mesa. The bridge connection trench is in fluid communication with each of the pair of vertical trenches. A bridge shield electrode is disposed in the bridge connection trench and is coupled to the shield electrode disposed below each of the gate electrodes in the pair of vertical trenches.

Abstract: An electronic device can include a substrate, an active region of a transistor, and a shield electrode. The substrate can define a trench and include a mesa adjacent to the trench, and the shield electrode can be within the trench. In an embodiment, the electronic device can further include an active region of a transistor within the mesa and an insulating layer including a thicker section and a thinner section closer to a bottom of the trench. In another embodiment, the electronic device can include a body region and a doped region within the mesa and spaced apart from the body region by a semiconductor region. The doped region can have a dopant concentration that is higher than a dopant concentration of the semiconductor region and a portion of the substrate underlying the doped region.

Abstract: A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.

Abstract: An electronic device can include a substrate, an active region of a transistor, and a shield electrode. The substrate can define a trench and include a mesa adjacent to the trench, and the shield electrode can be within the trench. In an embodiment, the electronic device can further include an active region of a transistor within the mesa and an insulating layer including a thicker section and a thinner section closer to a bottom of the trench. In another embodiment, the electronic device can include a body region and a doped region within the mesa and spaced apart from the body region by a semiconductor region. The doped region can have a dopant concentration that is higher than a dopant concentration of the semiconductor region and a portion of the substrate underlying the doped region.

Abstract: Systems and methods of the disclosed embodiments include an electronic device that has a gate electrode for supplying a gate voltage, a source, a drain, and a channel doped to enable a current to flow from the drain to the source when a voltage is applied to the gate electrode. The electronic device may also include a gate insulator between the channel and the gate electrode. The gate insulator may include a first gate insulator section including a first thickness, and a second gate insulator section including a second thickness that is less than the first thickness. The gate insulator sections thereby improve the safe operating area by enabling the current to flow through the second gate insulator section at a lower voltage than the first gate insulator section.

Abstract: In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.

Abstract: An electronic device can include a substrate, an active region of a transistor, and a shield electrode. The substrate can define a trench and include a mesa adjacent to the trench, and the shield electrode can be within the trench. In an embodiment, the electronic device can further include an active region of a transistor within the mesa and an insulating layer including a thicker section and a thinner section closer to a bottom of the trench. In another embodiment, the electronic device can include a body region and a doped region within the mesa and spaced apart from the body region by a semiconductor region. The doped region can have a dopant concentration that is higher than a dopant concentration of the semiconductor region and a portion of the substrate underlying the doped region.

Abstract: In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.

Abstract: An electronic device can include a transistor having a gate electrode, a first portion, and a second portion, wherein along the gate electrode, the first portion of the transistor has a first gate-to-drain capacitance and a first gate-to-source capacitance, the second portion of the transistor has a second gate-to-drain capacitance and a second gate-to-source capacitance, and a ratio of the first gate-to-drain capacitance to the first gate-to-source capacitance is less than a ratio of the second gate-to-drain capacitance to the second gate-to-source capacitance.

Abstract: A semiconductor device structure includes a region of semiconductor material comprising a first conductivity type, an active region, and a termination region. A first active trench structure is disposed in the active region, and a second active trench structure is disposed in the active region and laterally separated from the first active trench by an active mesa region having a first width. A first termination trench structure is disposed in the termination region and separated from the second active trench by a transition mesa region having a second width and a higher carrier charge than that of the active mesa region. In one example, the second width is greater than the first width to provide the higher carrier charge. In another example, the dopant concentration in the transition mesa region is higher than that in the active mesa region to provide the higher carrier charge.

Abstract: A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.

Abstract: A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.

Abstract: Systems and methods of the disclosed embodiments include an electronic device that has a gate electrode for supplying a gate voltage, a source, a drain, and a channel doped to enable a current to flow from the drain to the source when a voltage is applied to the gate electrode. The electronic device may also include a gate insulator between the channel and the gate electrode. The gate insulator may include a first gate insulator section comprising a first thickness, and a second gate insulator section comprising a second thickness that is less than the first thickness. The gate insulator sections thereby improve the safe operating area by enabling the current to flow through the second gate insulator section at a lower voltage than the first gate insulator section.

Abstract: An electronic device can include a transistor having a gate electrode, a first portion, and a second portion, wherein along the gate electrode, the first portion of the transistor has a first gate-to-drain capacitance and a first gate-to-source capacitance, the second portion of the transistor has a second gate-to-drain capacitance and a second gate-to-source capacitance, and a ratio of the first gate-to-drain capacitance to the first gate-to-source capacitance is less than a ratio of the second gate-to-drain capacitance to the second gate-to-source capacitance.

Abstract: A method for forming a cascode rectifier structure includes providing a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are provided adjacent a major surface of the heterostructure and a control electrode is provided between the first and second current carrying electrode. A rectifier device is provided integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is provided further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes. The cascode rectifier structure is provided as a two terminal device.

Abstract: An electronic device can include a transistor having a gate electrode, a first portion, and a second portion, wherein along the gate electrode, the first portion of the transistor has a first gate-to-drain capacitance and a first gate-to-source capacitance, the second portion of the transistor has a second gate-to-drain capacitance and a second gate-to-source capacitance, and a ratio of the first gate-to-drain capacitance to the first gate-to-source capacitance is less than a ratio of the second gate-to-drain capacitance to the second gate-to-source capacitance.