Abstract: A double patterning method of manufacturing select gates and word lines is provided in the present invention, including forming first string patterns composed of word line patterns and select gate patterns on a target layer, forming a conformal spacer layer on first string patterns, wherein the spacer layer forms trenches between first string patterns, forming a fill layer filling up the trenches on the spacer layer, removing fill layer outside of the trenches, so that fill layer in the trenches forms second string patterns, wherein the second string patterns and the first string patterns are spaced apart, removing exposed spacer layer, so that the first string patterns and the second string patterns constitute target patterns spaced apart from each other on the target layer, and performing an etching process using those target patterns as a mask to remove exposed target layer, so as to form word lines and select gates.

Abstract: A memory structure including the following components is provided. A first dielectric layer is disposed on a substrate. A first memory cell includes a first conductive layer, a second conductive layer, a first channel layer, and a first charge storage layer. The first conductive layer and the second conductive layer are sequentially stacked on the first dielectric layer and are electrically insulated from each other. The first channel layer is disposed on one side of the first conductive layer and one side of the second conductive layer. The first charge storage layer is disposed between the first conductive layer and the first channel layer. A first bit line is disposed in the first dielectric layer and is connected to the first channel layer. A source line is disposed above the first channel layer and is connected to the first channel layer.

Abstract: A memory structure including a substrate and memory cells is provided. The memory cells are stacked on the substrate. Each memory cell includes a first conductive layer, a first gate, a second gate, a second conductive layer, a channel layer, and a first charge storage layer. The first conductive layer, the first gate, the second gate, and the second conductive layer are sequentially stacked. The first conductive layer and the first gate are electrically insulated from each other. The first gate and the second gate are electrically insulated from each other. The second gate and the second conductive layer are electrically insulated from each other. The first gate and the second gate are electrically insulated from the channel layer. The first conductive layer and the second conductive layer are electrically connected to the channel layer. The first charge storage layer is located between the first gate and the channel layer.

Abstract: An non-volatile static random access memory (nvSRAM) is provided in the present invention, including a first pass gate transistor, a second pass gate transistor, a first pull-up transistor, a second pull-up transistor, a first pull-down transistor and a second pull-down transistor, which construct collectively two cross-coupled inverters with two storage nodes, wherein resistive random-access memories (RRAM) are set between the first storage node, the first pull-up transistor and the first pull-down transistor and between the second storage node, the second pull-up transistor and the second pull-down transistor.

Abstract: A memory structure including a substrate and memory cells is provided. The memory cells are stacked on the substrate. Each memory cell includes a first conductive layer, a first gate, a second gate, a second conductive layer, a channel layer, and a first charge storage layer. The first conductive layer, the first gate, the second gate, and the second conductive layer are sequentially stacked. The first conductive layer and the first gate are electrically insulated from each other. The first gate and the second gate are electrically insulated from each other. The second gate and the second conductive layer are electrically insulated from each other. The first gate and the second gate are electrically insulated from the channel layer. The first conductive layer and the second conductive layer are electrically connected to the channel layer. The first charge storage layer is located between the first gate and the channel layer.

Abstract: A 3D NAND flash memory device includes a substrate, a source line on the substrate, a stacked structure on the source line, a bit line on the stacked structure, and a columnar channel portion. The stacked structure includes a first select transistor, memory cells, and a second select transistor, wherein the first select transistor includes a first select gate, the memory cells include control gates, and the second select transistor includes a second select gate. The columnar channel portion is extended axially from the source line and penetrates the stacked structure to be coupled to the bit line. The first select transistor includes a modified Schottky barrier (MSB) transistor to generate direct tunneling of majority carriers to the columnar channel portion to perform a program operation or an erase operation.

Abstract: A hybrid memory structure including a substrate, a flash memory, a first resistive random access memory (RRAM), and a second RRAM is provided. The flash memory is located on the substrate. The flash memory includes a gate, a first doped region, and a second doped region. The gate is located on the substrate. The first doped region is located in the substrate on one side of the gate. The second doped region is located in the substrate on another side of the gate. The first RRAM is electrically connected to one of the gate, the first doped region, and the second doped region. The second RRAM is electrically connected to another of the gate, the first doped region, and the second doped region.

Abstract: A semiconductor patterning process includes the following steps. A substrate is provided, wherein the substrate has a first region, a second region, and a third region, and the second region is located between the first region and the third region. A plurality of initial mask patterns are formed on the substrate. A first mask material layer is conformally formed on the substrate. A first mask pattern is formed above at least two adjacent initial mask patterns in the second region and on the first mask material layer in between, and a second mask pattern is formed on the first mask material layer on sidewalls of remaining initial mask patterns. A portion of the first mask material layer is removed using the first mask pattern and the second mask pattern as a mask to form a final mask pattern on the substrate.

Abstract: A 3D NAND flash memory device includes a substrate, a source line on the substrate, a stacked structure on the source line, a bit line on the stacked structure, and a columnar channel portion. The stacked structure includes a first select transistor, memory cells, and a second select transistor, wherein the first select transistor includes a first select gate, the memory cells include control gates, and the second select transistor includes a second select gate. The columnar channel portion is extended axially from the source line and penetrates the stacked structure to be coupled to the bit line. The first select transistor includes a modified Schottky barrier (MSB) transistor to generate direct tunneling of majority carriers to the columnar channel portion to perform a program operation or an erase operation.

Abstract: A hybrid memory structure including a substrate, a flash memory, a first resistive random access memory (RRAM), and a second RRAM is provided. The flash memory is located on the substrate. The flash memory includes a gate, a first doped region, and a second doped region. The gate is located on the substrate. The first doped region is located in the substrate on one side of the gate. The second doped region is located in the substrate on another side of the gate. The first RRAM is electrically connected to one of the gate, the first doped region, and the second doped region. The second RRAM is electrically connected to another of the gate, the first doped region, and the second doped region.

Abstract: A semiconductor patterning process includes the following steps. A substrate is provided, wherein the substrate has a first region, a second region, and a third region, and the second region is located between the first region and the third region. A plurality of initial mask patterns are formed on the substrate. A first mask material layer is conformally formed on the substrate. A first mask pattern is formed above at least two adjacent initial mask patterns in the second region and on the first mask material layer in between, and a second mask pattern is formed on the first mask material layer on sidewalls of remaining initial mask patterns. A portion of the first mask material layer is removed using the first mask pattern and the second mask pattern as a mask to form a final mask pattern on the substrate.

Abstract: A non-volatile memory structure including a substrate, a stacked structure, a conductive pillar, a channel layer, a charge storage structure, and a second dielectric layer is provided. The stacked structure is disposed on the substrate and has an opening. The stacked structure includes first conductive layers and first dielectric layers alternately stacked. The conductive pillar is disposed in the opening. The channel layer is disposed between the stacked structure and the conductive pillar. The charge storage structure is disposed between the stacked structure and the channel layer. The second dielectric layer is disposed between the channel layer and the conductive pillar. The non-volatile memory structure can effectively improve the electrical performance and the reliability of the memory device.

Abstract: A resistive random access memory including a stacked structure, at least one vertical electrode, a selector element, and a plurality of resistance changeable structures is provided. The stacked structure is formed by a plurality of horizontal electrodes and a plurality of first dielectric layers stacked alternately, wherein the stacked structure has at least one channel hole extending through the horizontal electrodes and the first dielectric layers. The vertical electrode is formed in the at least one channel hole. The selector element is formed in the channel hole between the vertical electrode and the stacked structure. The resistance changeable structures are disposed on the surface of each of the horizontal electrodes and are in contact with the selector element in the channel hole.

Abstract: A non-volatile memory structure including a substrate, a stacked structure, a conductive pillar, a channel layer, a charge storage structure, and a second dielectric layer is provided. The stacked structure is disposed on the substrate and has an opening. The stacked structure includes first conductive layers and first dielectric layers alternately stacked. The conductive pillar is disposed in the opening. The channel layer is disposed between the stacked structure and the conductive pillar. The charge storage structure is disposed between the stacked structure and the channel layer. The second dielectric layer is disposed between the channel layer and the conductive pillar. The non-volatile memory structure can effectively improve the electrical performance and the reliability of the memory device.

Abstract: A resistive random access memory including a stacked structure, at least one vertical electrode, a selector element, and a plurality of resistance changeable structures is provided. The stacked structure is formed by a plurality of horizontal electrodes and a plurality of first dielectric layers stacked alternately, wherein the stacked structure has at least one channel hole extending through the horizontal electrodes and the first dielectric layers. The vertical electrode is formed in the at least one channel hole. The selector element is formed in the channel hole between the vertical electrode and the stacked structure. The resistance changeable structures are disposed on the surface of each of the horizontal electrodes and are in contact with the selector element in the channel hole.

Abstract: A manufacturing method of a non-volatile memory structure including the following steps is provided. Memory cells are formed on a substrate. An isolation layer is formed between the memory cells. A shield electrode is formed on the isolation layer. The shield electrode is electrically connected to a source line.

Abstract: A manufacturing method of a non-volatile memory structure including the following steps is provided. Memory cells are formed on a substrate. An isolation layer is formed between the memory cells. A shield electrode is formed on the isolation layer. The shield electrode is electrically connected to a source line.

Abstract: An integrated circuit structure including a substrate, a stacked structure, and first contacts is provided. The stacked structure is disposed on the substrate and includes first dielectric layers and conductive layers alternately stacked. The stacked structure has openings passing through the conductive layers. The first contacts are located in the openings. Bottoms of the first contacts are located at different heights. The first contacts and the conductive layers are electrically connected in a one-to-one manner. The first contacts and the conductive layers that are not electrically connected to each other are isolated from each other.

Abstract: A non-volatile memory structure including memory cells, at least one isolation layer, and at least one shield electrode is provided. The memory cells are disposed on a substrate. The isolation layer is located between the memory cells. The shield electrode is disposed on the isolation layer and electrically connected to a source line.

Abstract: An integrated circuit structure including a substrate, a stacked structure, and first contacts is provided. The stacked structure is disposed on the substrate and includes first dielectric layers and conductive layers alternately stacked. The stacked structure has openings passing through the conductive layers. The first contacts are located in the openings. Bottoms of the first contacts are located at different heights. The first contacts and the conductive layers are electrically connected in a one-to-one manner. The first contacts and the conductive layers that are not electrically connected to each other are isolated from each other.