Patents by Inventor Zih-Song Wang

Zih-Song Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10483271
    Abstract: A non-volatile memory structure including memory cells, at least one isolation layer, and at least one shield electrode is provided. The memory cells are disposed on a substrate. The isolation layer is located between the memory cells. The shield electrode is disposed on the isolation layer and electrically connected to a source line.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 19, 2019
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Zih-Song Wang
  • Publication number: 20190259773
    Abstract: An integrated circuit structure including a substrate, a stacked structure, and first contacts is provided. The stacked structure is disposed on the substrate and includes first dielectric layers and conductive layers alternately stacked. The stacked structure has openings passing through the conductive layers. The first contacts are located in the openings. Bottoms of the first contacts are located at different heights. The first contacts and the conductive layers are electrically connected in a one-to-one manner. The first contacts and the conductive layers that are not electrically connected to each other are isolated from each other.
    Type: Application
    Filed: May 28, 2018
    Publication date: August 22, 2019
    Applicant: Powerchip Technology Corporation
    Inventor: Zih-Song Wang
  • Publication number: 20190206885
    Abstract: A non-volatile memory structure including memory cells, at least one isolation layer, and at least one shield electrode is provided. The memory cells are disposed on a substrate. The isolation layer is located between the memory cells. The shield electrode is disposed on the isolation layer and electrically connected to a source line.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 4, 2019
    Applicant: Powerchip Technology Corporation
    Inventor: Zih-Song Wang
  • Patent number: 10290644
    Abstract: A non-volatile memory structure including a substrate, at least one memory cell, a first doped region, a second doped region, and a third doped region is provided. The memory cell is disposed on the substrate and has a channel region located in the substrate. The first doped region, the second doped region, and the third doped region are sequentially disposed in the substrate in an arrangement direction toward the channel region, and the first doped region is farthest from the channel region. The first doped region and the third doped region are of a first conductive type, and the second doped region is of a second conductive type.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 14, 2019
    Assignee: Powerchip Technology Corporation
    Inventors: Chen-Liang Ma, Zih-Song Wang
  • Publication number: 20180286877
    Abstract: A non-volatile memory structure including a substrate, at least one memory cell, a first doped region, a second doped region, and a third doped region is provided. The memory cell is disposed on the substrate and has a channel region located in the substrate. The first doped region, the second doped region, and the third doped region are sequentially disposed in the substrate in an arrangement direction toward the channel region, and the first doped region is farthest from the channel region. The first doped region and the third doped region are of a first conductive type, and the second doped region is of a second conductive type.
    Type: Application
    Filed: June 14, 2017
    Publication date: October 4, 2018
    Applicant: Powerchip Technology Corporation
    Inventors: Chen-Liang Ma, Zih-Song Wang
  • Patent number: 9460933
    Abstract: A patterning method is provided. Mask structures including first mask layers and first photoresist layers are formed sequentially on a material layer. A second mask layer covering the mask structures is conformally formed on the material layer. First sacrificed layers are formed between the mask structures. Parts of the second mask layer are removed to expose the first photoresist layers and form first U-shape mask layers. The first photoresist layers and the first sacrificed layers are removed. A third mask layer having first surfaces and second surfaces lower than the first surfaces is conformally formed on the material layer. Second sacrificed layers are formed on the second surfaces. Parts of the third mask layer are removed to expose protrusions of the first U-shape mask layers and form second U-shape mask layers. The material layer is patterned by using protrusions of the second U-shape mask layers as masks.
    Type: Grant
    Filed: August 2, 2015
    Date of Patent: October 4, 2016
    Assignee: Powerchip Technology Corporation
    Inventor: Zih-Song Wang
  • Publication number: 20160181267
    Abstract: A non-volatile memory cell, a NAND-type non-volatile memory, and a method of manufacturing the same are provided. The method of manufacturing the non-volatile memory cell includes the following steps. An insulating layer, a first conductive layer, an inter-gate insulating layer, a second conductive layer, and a hard mask layer are formed on a substrate in order. The hard mask layer, the second conductive layer, the inter-gate insulating layer, and the first conductive layer are patterned to form a stacked gate structure. The insulating layer on the substrate at two sides of the stacked gate structure is removed until the surface of the substrate is exposed. A portion of the substrate at two sides of the stacked gate structure is removed to form two recesses in the substrate, and each of the recesses is extended below the stacked gate structure. A source/drain region is formed in the substrate below the recesses.
    Type: Application
    Filed: March 12, 2015
    Publication date: June 23, 2016
    Inventors: Chih-Yuan Chen, Zih-Song Wang, Hann-Ping Hwang, Tzung-Hua Ying, Yen-Cheng Fang
  • Publication number: 20160043032
    Abstract: A memory circuit structure includes a substrate, a plurality of word lines disposed and evenly-spaced on the substrate, wherein the width of said word lines is F, and a select gate adjacent to the word lines, wherein the width of the select gate is (7+4n)F, and n is zero or positive integer.
    Type: Application
    Filed: October 8, 2015
    Publication date: February 11, 2016
    Inventors: Zih-Song Wang, Chia-Ming Wu
  • Publication number: 20160035733
    Abstract: A NAND flash circuit structure includes two select gates disposed on a substrate, and an even number of spaced-apart word lines disposed between the two select gates. The select gate is provided with a first portion and a second portion. The thickness of the first portion and the second portion are different.
    Type: Application
    Filed: October 12, 2015
    Publication date: February 4, 2016
    Inventors: Shu-Cheng Lin, Zih-Song Wang, Yi-Shiang Chang
  • Patent number: 9245766
    Abstract: A semiconductor process for manufacturing particular patterns includes the steps of forming a target layer and evenly-spaced core bodies on a substrate, conformally forming a hard mask layer, forming a first photoresist covering a predetermined region on the hard mask layer wherein the predetermined region encompasses at least two core bodies, performing a first etch process to remove a portion of the hard mask layer outside the predetermined region and expose a number of core bodies, removing the exposed core bodies, forming a second photoresist at least encompassing all the recesses in the predetermined region, and performing a second etch process to pattern the target layer.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: January 26, 2016
    Assignee: Powerchip Technology Corporation
    Inventors: Zih-Song Wang, Chia-Ming Wu
  • Patent number: 9196623
    Abstract: A semiconductor circuit structure and process of making the same is provided in the present invention, comprising the steps of providing a substrate having a target layer and a hard mask layer, forming a patterned small core body group and a large core body group on the hard mask layer, forming a spacer material layer conformally on the substrate and the core body groups, forming filling bodies in each recess of the spacer material layer, performing a first etching process to remove exposed spacer material layer, using the filling bodies as a mask to perform a second etching process for patterning the hard mask layer, and using the patterned hard mask layer as a mask to perform a third etching process for patterning the conductive layer.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: November 24, 2015
    Assignee: Powerchip Technology Corporation
    Inventors: Shu-Cheng Lin, Zih-Song Wang, Yi-Shiang Chang
  • Publication number: 20150137204
    Abstract: A semiconductor process for manufacturing particular patterns includes the steps of forming a target layer and evenly-spaced core bodies on a substrate, conformally forming a hard mask layer, forming a first photoresist covering a predetermined region on the hard mask layer wherein the predetermined region encompasses at least two core bodies, performing a first etch process to remove a portion of the hard mask layer outside the predetermined region and expose a number of core bodies, removing the exposed core bodies, forming a second photoresist at least encompassing all the recesses in the predetermined region, and performing a second etch process to pattern the target layer.
    Type: Application
    Filed: May 19, 2014
    Publication date: May 21, 2015
    Applicant: Powerchip Technology Corporation
    Inventors: Zih-Song Wang, Chia-Ming Wu
  • Patent number: 8883636
    Abstract: A semiconductor process for forming specific pattern features comprising the steps of forming a target layer, a hard mask layer and a plurality of equally spaced-apart core bodies on a substrate, forming spacers on sidewalls of the core bodies, removing the core bodies so that the spacers are spaced-apart on the hard mask layer, using spacers as a mask to pattern the hard mask layer, removing the hard mask bodies outside of a predetermined region, forming photoresists on several outermost hard mask bodies of the predetermined region, and using the photoresists and remaining hard mask bodies as a mask to pattern the target layer.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 11, 2014
    Assignee: Powerchip Technology Corporation
    Inventors: Zih-Song Wang, Shu-Cheng Lin, Yoshikazu Miyawaki
  • Publication number: 20140284678
    Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, word lines, select lines, and doped regions. The substrate includes a memory cell region and two select line regions located at two opposite sides of the memory cell region. The word lines are disposed in the memory cell region. The select lines are disposed in the select line regions. A line width of each of the word lines is equal to a line width of each of the select lines. A distance between the adjacent word lines, a distance between the adjacent select lines, and a distance between the adjacent select line and word line are equal to one another. The doped regions are located in the substrate at two sides of each of the word lines and at two sides of each of the select line regions.
    Type: Application
    Filed: June 20, 2013
    Publication date: September 25, 2014
    Inventors: Hui-Huang Chen, Chih-Yuan Chen, Zih-Song Wang
  • Publication number: 20130264622
    Abstract: A semiconductor circuit structure and process of making the same is provided in the present invention, comprising the steps of providing a substrate having a target layer and a hard mask layer, forming a patterned small core body group and a large core body group on the hard mask layer, forming a spacer material layer conformally on the substrate and the core body groups, forming filling bodies in each recess of the spacer material layer, performing a first etching process to remove exposed spacer material layer, using the filling bodies as a mask to perform a second etching process for patterning the hard mask layer, and using the patterned hard mask layer as a mask to perform a third etching process for patterning the conductive layer.
    Type: Application
    Filed: September 5, 2012
    Publication date: October 10, 2013
    Inventors: Shu-Cheng Lin, Zih-Song Wang, Yi-Shiang Chang
  • Publication number: 20130260557
    Abstract: A semiconductor process for forming specific pattern features comprising the steps of forming a target layer, a hard mask layer and a plurality of equally spaced-apart core bodies on a substrate, forming spacers on sidewalls of the core bodies, removing the core bodies so that the spacers are spaced-apart on the hard mask layer, using spacers as a mask to pattern the hard mask layer, removing the hard mask bodies outside of a predetermined region, forming photoresists on several outermost hard mask bodies of the predetermined region, and using the photoresists and remaining hard mask bodies as a mask to pattern the target layer.
    Type: Application
    Filed: September 12, 2012
    Publication date: October 3, 2013
    Inventors: Zih-Song Wang, Shu-Cheng Lin, Yoshikazu Miyawaki