Abstract: The present invention is directed to an STT-MRAM device including a plurality of magnetic tunnel junction (MTJ) memory elements. Each of the memory elements comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween; and a magnetic fixed layer separated from the magnetic reference layer structure by an anti-ferromagnetic coupling layer.

Abstract: The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto.

Abstract: A spin-torque transfer magnetic random access memory (STTMRAM) element employed to store a state based on the magnetic orientation of a free layer, the STTMRAM element is made of a first perpendicular free layer (PFL) including a first perpendicular enhancement layer (PEL). The first PFL is formed on top of a seed layer. The STTMRAM element further includes a barrier layer formed on top of the first PFL and a second perpendicular reference layer (PRL) that has a second PEL, the second PRL is formed on top of the barrier layer. The STTMRAM element further includes a capping layer that is formed on top of the second PRL.

Abstract: A spin transfer torque magnetic random access memory (STTMRAM) magnetic tunnel junction (MTJ) stack includes layers to which when electric current is applied cause switching of the direction of magnetization of at least one of the layer. The STTMRAM MTJ stack includes a reference layer (RL) with a direction of magnetization that is fixed upon manufacturing of the STTMRAM MTJ stack, a junction layer (JL) formed on top of the RL, a free layer (FL) formed on top of the JL. The FL has a direction of magnetization that is switchable relative to that of the RL upon the flow of electric current through the spin transfer torque magnetic random access memory (STTMRAM) magnetic tunnel junction (MTJ) stack. The STTMRAM MTJ stack further includes a spin confinement layer (SCL) formed on top of the FL, the SCL made of ruthenium.

Abstract: A spin-torque transfer memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.

Abstract: A testing method is described for performing a fast bit-error rate (BER) measurement on resistance-based RAM cells, such MTJ cells, at the wafer or chip level. Embodiments use one or more specially designed test memory cells fabricated with direct electrical connections between the two electrodes of the cell and external contact pads (or points) on the surface of the wafer (or chip). In the test setup the memory cell is connected an impedance mismatched transmission line through a probe for un-buffered, fast switching of the cell between the high and low resistance states without the need for CMOS logic to select and drive the cell. The unbalanced transmission line is used generate signal reflections from the cell that are a function of the resistance state. The reflected signal is used to detect whether the test cell has switched as expected.

Abstract: A spin-transfer torque memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.

Abstract: A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. The high resistance state of the MRLC occurs when the switchable reference and common free layers have opposite magnetization orientations. The low resistance state occurs when the orientations are the same. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. The SRL is switched with reference to the CFL by a voltage effect generated by a selected longer voltage pulse that does not switch the CFL.

Abstract: A checking mechanism for complete full-chip ESD protection circuit design and layout verification at layout level identifies all of both intentional and parasitic ESD devices contained in the design layout file and compiles a netlist. The checking mechanism then determines the critical operating parameters of the identified ESD devices and determines if the parasitic devices will negatively effect ESD protection performance. The checking mechanism then determines if the intentional devices meet design specifications; eliminates parasitic devices which will not negatively effect ESD protection from the netlist, and retains those parasitic devices which may lead to ESD protection malfunction. Design layout verification and faults are then reported.

Abstract: A checking mechanism for complete full-chip ESD protection circuit design and layout verification at layout level identifies all of both intentional and parasitic ESD devices contained in the design layout file and compiles a netlist. The checking mechanism then determines the critical operating parameters of the identified ESD devices and determines if the parasitic devices will negatively effect ESD protection performance. The checking mechanism then determines if the intentional devices meet design specifications; eliminates parasitic devices which will not negatively effect ESD protection from the netlist, and retains those parasitic devices which may lead to ESD protection malfunction. Design layout verification and faults are then reported.

Abstract: An all-mode, bonding pad-oriented ESD (electrostatic discharge) protection structure, protects ICs against ESD pulses of all modes in all directions. A unique quasi-symmetrical layout design is devised to improve ESD structure. Physical symmetry and rounded layout provide uniform current and thermal distribution as well as symmetrical electrical operation characteristics. The ESD structure allows tunable triggering voltage, low holding voltage, low impedance, low leakage, fast response time and low parasitic effect. The ESD structure can easily be placed under or surrounding a bonding pad and consumes little extra silicon. The ESD structure can be implemented in commercial BiCMOS processes and is suitable for multiple-supply, mixed-signal, parasitic-sensitive RF and high-pin-count ICs.

Abstract: An all-mode, bonding pad-oriented ESD (electrostatic discharge) protection structure, protects ICs against ESD pulses of all modes in all directions. A unique quasi-symmetrical layout design is devised to improve ESD structure. Physical symmetry and rounded layout provide uniform current and thermal distribution as well as symmetrical electrical operation characteristics. The ESD structure allows tunable triggering voltage, low holding voltage, low impedance, low leakage, fast response time and low parasitic effect. The ESD structure can easily be placed under or surrounding a bonding pad and consumes little extra silicon. The ESD structure can be implemented in commercial BiCMOS processes and is suitable for multiple-supply, mixed-signal, parasitic-sensitive RF and high-pin-count ICs.

Abstract: An overvoltage/overcurrent electrostatic discharge protection single circuit structure for Integrated Circuits protects on all paths and polarities between In/Out, Supply, and Ground pins. The structure is built on the chip substrate with an N well with three P Diffusions therein each containing N+ and P+ diffusions therein to form 6 transistors and 8 parasitic resistors to yield 5 thyristors. The structure provides very fast, symmetrical, full protection while using minimal chip area.