Abstract: A system and method using a single-minor micro-electro-mechanical system (MEMS) two-dimensional (2D) scanning mirror assembly, and/or a digital micromirror device (DMD having a plurality of independently steerable minors) for steering a plurality of light beams that include one or more light beam(s) for the headlight beam(s) of a vehicle and/or one or more light beam(s) for LiDAR purposes, along with highly effective associated devices for light-wavelength conversion, light dumping and heatsinking. Some embodiments include a digital camera, wherein image data from the digital camera and distance data from the LiDAR sensor are combined to provide information used to control the size, shape and direction of the smart headlight beam.

Abstract: A method of fabricating an organic memory device is provided. In the method, a bottom electrode is formed on a substrate. A first surface treatment is performed on the bottom electrode to form a bottom surface treatment layer on a surface thereof. A polymer thin film is formed on the bottom surface treatment layer, and a top electrode is formed on the polymer thin film.

Abstract: Electronic devices integrated on a single substrate and a method for fabricating the same are provided. The method includes providing a substrate, and forming at least two electronic devices on the substrate, wherein the at least two electronic devices are selected from a thin film transistor, a memory, a diode, a capacitor, a resistor and an inductor. The at least two electronic devices are formed from a plurality of film layers, each film layer is formed over the substrate at the same time, and at least one layer of the film layers is formed by printing process.

Abstract: The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate.

Abstract: An electronic device, e.g., a printed transistor device, comprises a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The substrate has a first platform and a second platform embossing on the surface thereof, and the first and second platforms are separated by a gap whose width is equivalent to the channel length of the transistor. The first and second conductive layers serving as the source and the drain, respectively, of the transistor device are formed on surfaces of the first and second platforms. The semiconductor layer is formed on the surface of the substrate in the gap.

Abstract: A method of fabricating an electronic device is disclosed. The method of fabricating an electronic device comprises providing a substrate. A first conductive layer is formed on the substrate. A silylation polyphenol (PVP) dielectric layer is formed on the first conductive layer. A patterned second conductive layer is formed on the silylation PVP dielectric layer.

Abstract: A nano compound. The nano compound includes a metal or oxide thereof and an organic compound capable of oxidation and reduction bonded to the metal or oxide thereof. The invention also provides an organic memory device including the nano compound.

Abstract: A method of fabricating an organic memory device is provided. In the method, a bottom electrode is formed on a substrate. A first surface treatment is performed on the bottom electrode to form a bottom surface treatment layer on a surface thereof. A polymer thin film is formed on the bottom surface treatment layer, and a top electrode is formed on the polymer thin film.

Abstract: An electronic device, e.g., a printed transistor device, comprises a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The substrate has a first platform and a second platform embossing on the surface thereof, and the first and second platforms are separated by a gap whose width is equivalent to the channel length of the transistor. The first and second conductive layers serving as the source and the drain, respectively, of the transistor device are formed on surfaces of the first and second platforms. The semiconductor layer is formed on the surface of the substrate in the gap.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a semiconductor device formed with a plurality of transistors; forming a first stress layer with a plurality of layers on the semiconductor device; forming a second stress layer with a plurality of layers on another surface of the semiconductor device; covering photo resist on a region of the first stress layer to cover at least one of the transistors; and performing ion implantation on the part of the semiconductor device that is not covered by the photo resist. In another embodiment, the second stress layers can be formed after the ion implantation. The method can simultaneously enhance the device performance of the PMOS and NMOS on the same wafer. It also solves the problem of procedure integration caused by the produced compressive stress and tensile stress.

Abstract: An electronic device, e.g., a printed transistor device, comprises a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The substrate has a first platform and a second platform embossing on the surface thereof, and the first and second platforms are separated by a gap whose width is equivalent to the channel length of the transistor. The first and second conductive layers serving as the source and the drain, respectively, of the transistor device are formed on surfaces of the first and second platforms. The semiconductor layer is formed on the surface of the substrate in the gap.

Abstract: The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate.

Abstract: A method for fabricating a semiconductor device is provided. The method mainly involves steps of forming at least one first patterned high stress layer below a silicon substrate, then forming a semiconductor device onto the substrate, and forming at least one second patterned high stress layer on the semiconductor device. According to the method, the characteristics of the PMOS and the NMOS transistors formed on the same wafer may be improved simultaneously, by utilizing the stress of the patterned layers of high stress material. Further, the mobility of the carriers is enhanced, so that the output characteristic of the transistors can be improved.

Abstract: A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.

Abstract: An RFID tag system comprises at least one RFID tag and a reader. The RFID tag outputs a data stream including a head with a plurality of bits set to a sequence of certain levels and a body succeeding the head. The reader can detect the coding frequency of the data stream outputted from the RFID tag according to the known levels in the sequence, and then, read the body data based on the detected frequency.

Abstract: A method of fabricating an electronic device is disclosed. The method of fabricating an electronic device comprises providing a substrate. A first conductive layer is formed on the substrate. A silylation polyphenol (PVP) dielectric layer is formed on the first conductive layer. A patterned second conductive layer is formed on the silylation PVP dielectric layer.

Abstract: Electronic devices integrated on a single substrate and a method for fabricating the same are provided. The method includes providing a substrate, and forming at least two electronic devices on the substrate, wherein the at least two electronic devices are selected from a thin film transistor, a memory, a diode, a capacitor, a resistor and an inductor. The at least two electronic devices are formed from a plurality of film layers, each film layer is formed over the substrate at the same time, and at least one layer of the film layers is formed by printing process.

Abstract: An electronic device, e.g., a printed transistor device, comprises a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The substrate has a first platform and a second platform embossing on the surface thereof, and the first and second platforms are separated by a gap whose width is equivalent to the channel length of the transistor. The first and second conductive layers serving as the source and the drain, respectively, of the transistor device are formed on surfaces of the first and second platforms. The semiconductor layer is formed on the surface of the substrate in the gap.

Abstract: A nano compound. The nano compound includes a metal or oxide thereof and an organic compound capable of oxidation and reduction bonded to the metal or oxide thereof. The invention also provides an organic memory device including the nano compound.

Abstract: A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device comprises a substrate. A polyacrylonitrile (PAN) powder is dissolved in a solvent and the solvent is heated to form a PAN solution. The PAN solution is cooled down and the PAN solution is then formed on the substrate. The PAN solution is allowed to stand and the solvent in the PAN solution is then removed to form a PAN dielectric layer on the substrate. A patterned conductive layer is formed on the PAN dielectric layer.