Abstract: An organic memory device includes a top electrode, a bottom electrode, and a bistable organic polymer layer between the top and bottom electrodes. Moreover, the organic memory device further includes a surface treatment layer between the organic polymer layer and the bottom electrode. Because the surface treatment layer can stabilize the interface between the organic polymer layer and the bottom electrode, the reliability of the device may be promoted.

Abstract: A method for manufacturing a carbon nano-tube field-effect transistor (CNT-FET), comprising steps of: forming a patterned conductive layer on a substrate; forming a dielectric layer covering the conductive layer and the substrate; forming a carbon nano-tube layer between a pair of electrodes on the dielectric layer; and performing a treatment process on the carbon nano-tube layer so that the carbon nano-tube layer is semiconducting.

Abstract: A semiconductor device with transistors and a fabricating method therefore are provided. The electrodes of the transistors are formed on the same layer, and they are coupled to one another by a conductor layer. Therefore, the requirement for the vias in whole circuit is reduced, and the cost is decreased.

Abstract: The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate.

Abstract: A semiconductor structure and method for manufacturing the same is disclosed. The present invention relates to a semiconductor having a dielectric layer applied on a gate of a transistor, and a high dielectric-coefficient, and a manufacturing method of the semiconductor. Ti is formed on HfO2 to absorb oxygen from the dielectric layer to reduce its thickness, and even make it disappear. However, the TiO2 grown on the layer of Ti advances the growing of HfO2. Simultaneously, the dielectric constant of TiO2 is about 50. The TiO2 substantially enhances the dielectric constant for the dielectric layer. Ti absorbs the oxygen to reduce its thickness and increase the dielectric constant to reduce EOT. Moreover, TiO2 is formed and the dielectric constant is increased after heating. Accordingly, leakage is avoided in the TiO2. The present invention enhances the applications for high-k gate dielectrics with high electric constants, and continuously reduces the EOT.

Abstract: An organic thin film transistor and a method for fabricating the same are provided. A multi-dielectric layer of the organic thin-film transistor is disposed on the substrate and the gate electrode, and then the organic layers-of the organic thin film transistor, the source and drain are produced. Because of the isolation effect of the multi-dielectric layer, the hydrophilic and lipophilic processes do not affect each other during the manufacturing of the organic thin film transistor. In addition, the multi-dielectric layer includes at least one organic dielectric layer and at least one liquid state deposited oxide silicon thin film.

Abstract: A method for fabricating a semiconductor device is provided. The method mainly involves steps of forming at least one first patterned high stress layer below a silicon substrate, then forming a semiconductor device onto the substrate, and forming at least one second patterned high stress layer on the semiconductor device. According to the method, the characteristics of the PMOS and the NMOS transistors formed on the same wafer may be improved simultaneously, by utilizing the stress of the patterned layers of high stress material. Further, the mobility of the carriers is enhanced, so that the output characteristic of the transistors can be improved.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a semiconductor device formed with a plurality of transistors; forming a first stress layer with a plurality of layers on the semiconductor device; forming a second stress layer with a plurality of layers on another surface of the semiconductor device; covering photo resist on a region of the first stress layer to cover at least one of the transistors; and performing ion implantation on the part of the semiconductor device that is not covered by the photo resist. In another embodiment, the second stress layers can be formed after the ion implantation. The method can simultaneously enhance the device performance of the PMOS and NMOS on the same wafer. It also solves the problem of procedure integration caused by the produced compressive stress and tensile stress.

Abstract: A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.

Abstract: A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.

Abstract: A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.

Abstract: A phototransistor structure is disclosed. A sidewall is grown on the collector side and under the base. The surface of the sidewall is formed with a sidewall contact. When the contact is connected to an external voltage, the holes accumulated at the junction of the base and emitter can be quickly removed. This solves the problem in the prior art that using a bias between the base and the emitter to remove holes usually results in a large dark current (bias current), power consumption, and diminishing optoelectronic conversion gain.