Abstract: Augmented-domain simulation, such as ternary-based simulation may be utilized to approximate a reachability analysis of a model being model checked. The approximated reachability analysis may be utilized to detect design redundancies and modify the model to remove such redundancies. Design redundancies may include unobservable variables, mergeable variables and utilization of surplus domains.

Abstract: A model may comprise finite paths in respect to a constraint. The model and the constraint may be modified such that a portion of the limitations induces by the constraint is injected to the model. Adding the limitation directly to the model may be expressed by a reduction of a measurement of nondeterminism in the model. The model may be modified based on the constraint, and the constraint may be modified based on the model. The constraint may be strengthened to provide for an early finite path detection.

Abstract: Phase abstraction may be utilized to increase efficiency of model checking techniques. A liveness property may be checked in respect to a phase abstracted model by modifying the liveness property in accordance with the phase abstracted model. A fairness property may be modified to ensure that the fairness property is held by the model checker. A counter-example produced by a model checker is modified to be in accordance to an original model. The counter-example comprises a repetitive behavior. The counter-example may be modified to shorten the repetitive behavior or to apply the repetitive behavior in an earlier cycle of the counter-example.

Abstract: Computer-implemented techniques are disclosed for defining an environment for formal verification of a design-under-test. Initially there is extraction of design inputs by a design analysis module, and presentation of the inputs on a graphical user interface. Behavior options for the design inputs are offered on the graphical user interface for selection by an operator. Environment code that is descriptive of the design inputs and selected behavior options is emitted, typically in a hardware description language, for submission to a formal verification tool. A meta-code file containing the assigned behavior options is generated to aid subsequent sessions.

Abstract: Formal verification of models using concurrent model-reduction and model-checking. For example, a system for formal verification of models includes: one or more model reducers to reduce a model; one or more model checkers to check the model, wherein at least one of the model reducers is to run concurrently with at least one of the model checkers; and a model synchronizer to synchronize information between at least one of the model reducers and at least one of the model checkers.

Abstract: A portable communication device such a mobile phone is disclosed which may be configured to communicate using a wireless personal area network (WPAN) protocol and one or more wireless local area network (WLAN), wireless metropolitan area network (WMAN) or wireless wide area network (WWAN) protocols. The portable communication device includes a port to store and/or charge a separate WPAN device such as a wireless headset and in certain embodiments, the port may charge a battery of wireless headset so that both the portable communication device and wireless headset may be carried as an integrated single unit and/or charged using a single charging cord. Additional embodiments and variations are also disclosed.

Abstract: A method for design verification includes running a simulation of a design in a simulation environment, which comprises a stimuli generator for providing inputs to the design during the simulation. Respective measures of quality are computed for at least some of the simulation states in a sequence of states generated by the environment. State data are saved with respect to at least one of the simulation states. The state data include indications both of the respective simulated state and of the respective environment state. Responsively to the respective measures of quality, the saved state data are recalled so as to restart the simulation from the at least one of the simulation states by returning the design to the respective simulated state and returning the simulation environment to the respective environment state.

Abstract: A method for verification of a system design represented by a model that includes a plurality of variables. The method includes arranging the variables in an Ordered Binary Decision Diagram (OBDD) according to an initial order of the variables, the OBDD including a number of nodes arranged in rows corresponding respectively to the plurality of the variables. Each processor, among a group of two or more computer processors, is assigned a respective variable among the plurality of the variables. Using each processor, the rows of the OBDD are reordered by varying a position in the OBDD of the row corresponding to the respective variable that is assigned to the processor until at least one of the processors identifies a new order for the OBDD. The new order of the OBDD may be used to verify a characteristic of the model against a specification.

Abstract: A method for verification of a system design represented by a model that includes a plurality of variables. The method includes arranging the variables in an Ordered Binary Decision Diagram (OBDD) according to an initial order of the variables, the OBDD including a number of nodes arranged in rows corresponding respectively to the plurality of the variables. Each processor, among a group of two or more computer processors, is assigned a respective variable among the plurality of the variables. Using each processor, the rows of the OBDD are reordered by varying a position in the OBDD of the row corresponding to the respective variable that is assigned to the processor until at least one of the processors identifies a new order for the OBDD. The new order of the OBDD may be used to verify a characteristic of the model against a specification.