Patents by Inventor Ziwei Fang

Ziwei Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10811253
    Abstract: A method of fabricating semiconductor devices is provided. The method includes forming an interfacial layer on a substrate, and depositing a gate dielectric layer on the interfacial layer. The method also includes treating the gate dielectric layer with a first post deposition annealing (PDA) process. The method further includes depositing a first capping layer on the gate dielectric layer, and treating the gate dielectric layer by performing a post metal annealing (PMA) process on the first capping layer. In addition, the method includes removing the first capping layer, and treating the gate dielectric layer with a second PDA process. The method also includes forming a gate electrode layer on the gate dielectric layer.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Publication number: 20200328213
    Abstract: A semiconductor device is provided. The semiconductor device includes first nanostructures vertically stacked over a first region of a substrate, a gate dielectric layer wrapping around the first nanostructures, a first oxygen blocking layer wrapping around the gate dielectric layer in the first region, a first-type work function layer wrapping around the first oxygen blocking layer in the first region, a second oxygen blocking layer wrapping around the first-type work function layer in the first region, and a second-type work function layer wrapping around the second oxygen blocking layer in the first region.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang CHENG, Ziwei FANG
  • Publication number: 20200303549
    Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure extended above a substrate and forming a gate structure formed over a portion of the fin structure. The method also includes forming a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The method further includes doping an outer portion of the S/D structure to form a doped region, and the doped region includes gallium (Ga). The method includes forming a metal silicide layer over the doped region; and forming an S/D contact structure over the metal silicide layer.
    Type: Application
    Filed: June 11, 2020
    Publication date: September 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung TSAI, Shahaji B. MORE, Cheng-Yi PENG, Yu-Ming LIN, Kuo-Feng YU, Ziwei FANG
  • Publication number: 20200303260
    Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET) includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer including Si1?x?yM1xM2y, where M1 includes Sn, M2 is one or more of P and As, and 0.01?x?0.1, and 0.01?y?0.1.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Inventors: Yasutoshi OKUNO, Cheng-Yi PENG, Ziwei FANG, I-Ming CHANG, Akira MINEJI, Yu-Ming LIN, Meng-Hsuan HSIAO
  • Publication number: 20200303259
    Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET), the method includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer made of Si1-y-a-bGeaSnbM2y, wherein 0<a, 0<b, 0.01?(a+b)?0.1, 0.01?y?0.1, and M2 is P or As.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Inventors: Yasutoshi OKUNO, Cheng-Yi PENG, Ziwei FANG, I-Ming CHANG, Akira MINEJI, Yu-Ming LIN, Meng-Hsuan HSIAO
  • Publication number: 20200294865
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a work function material around a first semiconductor layer in a first region and a second semiconductor layer in a second region. The method also includes forming a first gate electrode material over the work function material. The method also includes removing the first gate electrode material in the first region. The method also includes forming a second gate electrode material over the work function material in the first region.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang CHENG, Ziwei FANG
  • Publication number: 20200294806
    Abstract: A semiconductor structure having metal contact features and a method for forming the same are provided. The method includes forming a dielectric layer covering an epitaxial structure over a semiconductor substrate and forming an opening in the dielectric layer to expose the epitaxial structure. The method includes forming a metal-containing layer over the dielectric layer and the epitaxial structure. The method includes heating the epitaxial structure and the metal-containing layer to transform a first portion of the metal-containing layer contacting the epitaxial structure into a metal-semiconductor compound layer. The method includes oxidizing the metal-containing layer to transform a second portion of the metal-containing layer over the metal-semiconductor compound layer into a metal oxide layer. The method includes applying a metal chloride-containing etching gas on the metal oxide layer to remove the metal oxide layer and forming a metal contact feature over the metal-semiconductor compound layer.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang CHENG, Ziwei FANG
  • Patent number: 10770563
    Abstract: A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Publication number: 20200279846
    Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. The at least one gate stack is disposed over the insulators and over the channel portions of the fins. The epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. The epitaxy material portions disposed on the flank portions of the fins are separate from one another.
    Type: Application
    Filed: April 20, 2020
    Publication date: September 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Tsai, Ziwei Fang, Tsan-Chun Wang, Kei-Wei Chen
  • Publication number: 20200279949
    Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Tsai, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
  • Publication number: 20200273700
    Abstract: A method of fabricating semiconductor devices is provided. The method includes forming an interfacial layer on a substrate, and depositing a gate dielectric layer on the interfacial layer. The method also includes treating the gate dielectric layer with a first post deposition annealing (PDA) process. The method further includes depositing a first capping layer on the gate dielectric layer, and treating the gate dielectric layer by performing a post metal annealing (PMA) process on the first capping layer. In addition, the method includes removing the first capping layer, and treating the gate dielectric layer with a second PDA process. The method also includes forming a gate electrode layer on the gate dielectric layer.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang CHENG, Ziwei FANG
  • Publication number: 20200268729
    Abstract: The present invention provides a compound represented by formula (I), or a pharmaceutically acceptable salt or prodrug thereof.
    Type: Application
    Filed: December 1, 2017
    Publication date: August 27, 2020
    Inventors: Ziwei HUANG, Xiong FANG, Qian MENG, Yan XU, Siyu ZHU, Xiao FANG
  • Publication number: 20200273985
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer over an inner wall and a bottom of the trench. The method includes forming a mask layer over the gate dielectric layer over the bottom. The method includes removing the gate dielectric layer over the inner wall. The method includes removing the mask layer. The method includes forming a gate electrode in the trench.
    Type: Application
    Filed: February 26, 2019
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang CHENG, Ziwei FANG
  • Patent number: 10749008
    Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Tsai, Kuo-Feng Yu, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
  • Publication number: 20200243522
    Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure including a stack of alternating first and second semiconductor layers on a substrate, removing the first semiconductor layers to form spaces between the second semiconductor layers, and depositing a gate dielectric layer to surround the second semiconductor layers. The method also includes depositing a first oxygen blocking layer and removing the native oxide thereof, depositing an n-type work function layer, and forming a second oxygen blocking layer in sequence on the gate dielectric layer to surround the second semiconductor layers in the same process chamber. The second oxygen blocking layer includes a capping layer and a capping film. The method further includes forming a metal gate fill material over the capping film to form a gate-all-around structure.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang CHENG, Ziwei FANG
  • Patent number: 10720529
    Abstract: A method includes forming a first channel region and a first gate structure formed over the first channel region. A first source/drain region is formed adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Sheng-Wen Yu, Ziwei Fang
  • Patent number: 10720431
    Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure including a stack of alternating first and second semiconductor layers on a substrate, removing the first semiconductor layers to form spaces between the second semiconductor layers, and depositing a gate dielectric layer to surround the second semiconductor layers. The method also includes depositing a first oxygen blocking layer and removing the native oxide thereof, depositing an n-type work function layer, and forming a second oxygen blocking layer in sequence on the gate dielectric layer to surround the second semiconductor layers in the same process chamber. The second oxygen blocking layer includes a capping layer and a capping film. The method further includes forming a metal gate fill material over the capping film to form a gate-all-around structure.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Patent number: 10707320
    Abstract: A method of forming a semiconductor device includes forming a hafnium-containing layer over a semiconductor layer, simultaneously performing a thermal annealing process and applying an electrical field to the hafnium-containing layer to form a ferroelectric hafnium-containing layer, and forming a gate electrode over the ferroelectric hafnium-containing layer.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ming Lin, Kai Tak Lam, Sai-Hooi Yeong, Chi On Chui, Ziwei Fang
  • Patent number: 10685867
    Abstract: A method of semiconductor device fabrication includes providing a substrate having a hardmask layer thereover. The hardmask layer is patterned to expose the substrate. The substrate is etched through the patterned hardmask layer to form a first fin element and a second fin element extending from the substrate. An isolation feature between the first and second fin elements is formed, where the isolation feature has a first etch rate in a first solution. A laser anneal process is performed to irradiate the isolation feature with a pulsed laser beam. A pulse duration of the pulsed laser beam is adjusted based on a height of the isolation feature. The isolation feature after performing the laser anneal process has a second etch rate less than the first etch rate in the first solution.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: De-Wei Yu, Tsu-Hsiu Perng, Ziwei Fang
  • Patent number: 10686074
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure extended above a substrate and a gate structure formed over a middle portion of the fin structure. The middle portion of the fin structure is wrapped by the gate structure. The FinFET device structure includes a source/drain (S/D) structure adjacent to the gate structure, and the S/D structure includes a doped region at an outer portion of the S/D structure, and the doped region includes gallium (Ga). The FinFET device structure includes a metal silicide layer formed over the doped region of the S/D structure, and the metal silicide layer is in direct contact with the doped region of the S/D structure.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Tsai, Shahaji B. More, Cheng-Yi Peng, Yu-Ming Lin, Kuo-Feng Yu, Ziwei Fang