Patents by Inventor Ziwei Fang

Ziwei Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200411662
    Abstract: A method of forming a semiconductor device includes forming a sacrificial layer on sidewalls of gate spacers disposed over a semiconductor layer, forming a first hafnium-containing gate dielectric layer over the semiconductor layer in a first trench disposed between the gate spacers, removing the sacrificial layer to form a second trench between the gate spacers and the first hafnium-containing gate dielectric layer, forming a second hafnium-containing gate dielectric layer over the first hafnium-containing gate dielectric layer and on the sidewalls of the gate spacers, annealing the first and the second hafnium-containing gate dielectric layers while simultaneously applying an electric field, and subsequently forming a gate electrode over the annealed first and second hafnium-containing gate dielectric layers.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Chi On Chui, Ziwei Fang, Huang-Lin Chao
  • Patent number: 10879246
    Abstract: A semiconductor device is provided. The semiconductor device includes first nanostructures vertically stacked over a first region of a substrate, a gate dielectric layer wrapping around the first nanostructures, a first oxygen blocking layer wrapping around the gate dielectric layer in the first region, a first-type work function layer wrapping around the first oxygen blocking layer in the first region, a second oxygen blocking layer wrapping around the first-type work function layer in the first region, and a second-type work function layer wrapping around the second oxygen blocking layer in the first region.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Publication number: 20200403078
    Abstract: A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Patent number: 10872970
    Abstract: Source and drain formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, wherein the fin structure include a channel region disposed between a source region and a drain region; forming a gate structure over the channel region of the fin structure; forming a solid phase diffusion (SPD) layer over the source region and the drain region of the fin structure; and performing a microwave annealing (MWA) process to diffuse a dopant from the SPD layer into the source region and the drain region of fin structure. In some implementations, the SPD layer is disposed over the fin structure, such that the dopant diffuses laterally and vertically into the source region and the drain region to form heavily doped source/drain features.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung Tsai, Kuo-Feng Yu, Ziwei Fang
  • Publication number: 20200395250
    Abstract: A method includes providing a channel region and growing an oxide layer on the channel region. Growing the oxide layer includes introducing a first source gas providing oxygen and introducing a second source gas providing hydrogen. The second source gas being different than the first source gas. The growing the oxide layer is grown by bonding the oxygen to a semiconductor element of the channel region to form the oxide layer and bonding the hydrogen to the semiconductor element of the channel region to form a semiconductor hydride byproduct. A gate dielectric layer and electrode can be formed over the oxide layer.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 17, 2020
    Inventors: Chung-Liang CHENG, I-Ming CHANG, Hsiang-Pi CHANG, Yu-Wei LU, Ziwei FANG, Huang-Lin CHAO
  • Patent number: 10868151
    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10868171
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer over an inner wall and a bottom of the trench. The method includes forming a mask layer over the gate dielectric layer over the bottom. The method includes removing the gate dielectric layer over the inner wall. The method includes removing the mask layer. The method includes forming a gate electrode in the trench.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Patent number: 10868140
    Abstract: A method includes depositing a silicon layer on a plurality of strips. The silicon layer is etched back to remove top portions of the silicon layer, and to expose some portions of the plurality of strips. Some bottom portions of the silicon layer at bottoms of trenches between the plurality of strips remain after the etching back. A germanium layer is selectively grown from remaining portions of the silicon layer, and exposed portions of the plurality of strips remain exposed after the germanium layer is selectively grown.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Ziwei Fang, Yee-Chia Yeo
  • Patent number: 10861751
    Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate, and forming a first layer including a first material over the first and second fin elements, wherein the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer, wherein performing the anneal process includes adjusting an energy applied to the first layer during the anneal process. The gap is filled by a portion of the first material around the gap reaching a sub-melt temperature that is different from a melting point of the first material.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: De-Wei Yu, Chia Ping Lo, Liang-Gi Yao, Weng Chang, Yee-Chia Yeo, Ziwei Fang
  • Publication number: 20200381529
    Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Inventors: Chun-Hsiung Tsai, Kuo-Feng Yu, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
  • Patent number: 10854503
    Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate and extending from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; removing the outer gate spacer in the isolation region, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Chang Sun, Akira Mineji, Ziwei Fang
  • Patent number: 10854729
    Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsan-Chun Wang, Ziwei Fang, Chii-Horng Li, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang
  • Publication number: 20200373206
    Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second nanostructured channel regions in first and second nanostructured layers, respectively, and first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The first GAA structure includes an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer. The second GAA structure includes an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.
    Type: Application
    Filed: January 10, 2020
    Publication date: November 26, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang CHENG, Ziwei FANG
  • Publication number: 20200373400
    Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.
    Type: Application
    Filed: November 21, 2019
    Publication date: November 26, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang CHENG, Ziwei Fang, Chun-I WU, Huang-Lin Chao
  • Patent number: 10847431
    Abstract: A method for fabricating a semiconductor device using a high-temperature ion implantation process includes providing a substrate including a plurality of fins. In some examples, a mask material is deposited and patterned to expose a group of fins of the plurality of fins and a test structure. By way of example, a first ion implantation may be performed, at a first temperature, through the group of fins and the test structure. Additionally, a second ion implantation may be performed, at a second temperature greater than the first temperature, through the group of fins and the test structure. In various examples, an interstitial cluster is formed within the group of fins and within the test structure. In some embodiments, an anneal process is performed, where the anneal process serves to remove the interstitial cluster from the group of fins and form at least one dislocation loop within the test structure.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsan-Chun Wang, Chun Hsiung Tsai, Ziwei Fang
  • Publication number: 20200350430
    Abstract: A method includes forming a first channel region and a first gate structure formed over the first channel region. A first source/drain region is formed adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Chun Hsiung Tsai, Sheng-Wen Yu, Ziwei Fang
  • Patent number: 10818768
    Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a semiconductor fin, forming a source/drain structure on the semiconductor fin, forming a gate electrode layer across the semiconductor fin, forming a first halogen-containing metal cap layer on the gate electrode layer, forming a contact structure on the source/drain structure and connected to the source/drain structure, and forming a second halogen-containing metal cap layer on the contact structure. The first halogen-containing metal cap layer and the second halogen-containing metal cap layer include different halogens.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Publication number: 20200335346
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming a spacer element over a sidewall of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess exposing a semiconductor strip and forming an inhibition layer over an interior surface of the spacer element. The method further includes forming a gate dielectric layer in the recess to selectively cover the semiconductor strip. The inhibition layer substantially prevents the gate dielectric layer from being formed on the inhibition layer. In addition, the method includes forming a metal gate electrode over the gate dielectric layer.
    Type: Application
    Filed: April 17, 2019
    Publication date: October 22, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Christine Y OUYANG, Ziwei FANG
  • Publication number: 20200335599
    Abstract: A semiconductor structure that includes a semiconductor fin disposed over a substrate, S/D features disposed over the semiconductor fin, and a metal gate stack interposed between the S/D features. The metal gate stack includes a gate dielectric layer disposed over the semiconductor fin, a capping layer disposed over the gate dielectric layer, and a gate electrode disposed over the capping layer, where the gate dielectric layer includes hafnium oxide with hafnium atoms and oxygen atoms arranged in a Pca21 space group.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Inventors: Cheng-Ming Lin, Kai Tak Lam, Sai-Hooi Yeong, Chi On Chui, Ziwei Fang
  • Patent number: 10811253
    Abstract: A method of fabricating semiconductor devices is provided. The method includes forming an interfacial layer on a substrate, and depositing a gate dielectric layer on the interfacial layer. The method also includes treating the gate dielectric layer with a first post deposition annealing (PDA) process. The method further includes depositing a first capping layer on the gate dielectric layer, and treating the gate dielectric layer by performing a post metal annealing (PMA) process on the first capping layer. In addition, the method includes removing the first capping layer, and treating the gate dielectric layer with a second PDA process. The method also includes forming a gate electrode layer on the gate dielectric layer.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang