Patents by Inventor Ziwei Fang
Ziwei Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230238443Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors.Type: ApplicationFiled: April 3, 2023Publication date: July 27, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Ming LIN, Sai-Hooi YEONG, Ziwei FANG, Chi On CHUI, Huang-Lin CHAO
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Patent number: 11710779Abstract: An integrated circuit device is provided that includes a first fin structure and a second fin structure extending from a substrate. The first fin structure is a first composition, and includes rounded corners. The second fin structure is a second composition, different than the first composition. A first interface layer is formed directly on the first fin structure including the rounded corners and a second interface layer directly on the second fin structure. The first interface layer is an oxide of the first composition and the second interface layer is an oxide of the second composition. A gate dielectric layer is formed over the first interface layer and the second interface layer.Type: GrantFiled: April 5, 2021Date of Patent: July 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Liang Cheng, I-Ming Chang, Hsiang-Pi Chang, Yu-Wei Lu, Ziwei Fang, Huang-Lin Chao
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Patent number: 11695006Abstract: In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.Type: GrantFiled: May 17, 2021Date of Patent: July 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tung Ying Lee, Ziwei Fang, Yee-Chia Yeo, Meng-Hsuan Hsiao
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Publication number: 20230207695Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.Type: ApplicationFiled: February 27, 2023Publication date: June 29, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Ming LIN, Sai-Hooi YEONG, Ziwei FANG, Chi On CHUI, Huang-Lin CHAO
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Patent number: 11688631Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate that extends from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; forming a mask layer over the substrate that exposes a portion of the ILD layer and a portion of the outer gate spacer; selectively etching the exposed portion of the outer gate spacer, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process on the exposed portion of the ILD layer to seal the air gap.Type: GrantFiled: July 7, 2022Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Chang Sun, Akira Mineji, Ziwei Fang
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Patent number: 11670694Abstract: The structure of a semiconductor device with dual metal capped via contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a source/drain (S/D) region and a gate structure on a fin structure, forming S/D and gate contact structures on the S/D region and the gate structure, respectively, forming first and second via contact structures on the S/D and gate contact structures, respectively, and forming first and second interconnect structures on the first and second via contact structures, respectively. The forming of the first and second via contact structures includes forming a first via contact plug interposed between first top and bottom metal capping layers and a second via contact plug interposed between second top and bottom metal capping layers, respectively.Type: GrantFiled: March 2, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Liang Cheng, Ziwei Fang
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Publication number: 20230131388Abstract: A semiconductor structure is provided. The semiconductor structure includes a first channel layer over a first region of a substrate, a first gate dielectric layer over the first channel layer, and a first gate electrode structure over the first gate dielectric layer. The first gate electrode structure includes a barrier layer over the first gate dielectric layer, a barrier oxide over and in contact with the barrier layer, and a metal fill layer over the barrier oxide. The barrier layer is made of a nitride of a metal, and the barrier oxide is made of an oxide of the metal.Type: ApplicationFiled: December 21, 2022Publication date: April 27, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Liang CHENG, Ziwei FANG
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Patent number: 11626493Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate. The silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer is thinner than the second metal-containing layer.Type: GrantFiled: June 11, 2021Date of Patent: April 11, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Wen Tsau, Chun-I Wu, Ziwei Fang, Huang-Lin Chao, I-Ming Chang, Chung-Liang Cheng, Chih-Cheng Lin
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Patent number: 11621338Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer.Type: GrantFiled: April 12, 2021Date of Patent: April 4, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Ziwei Fang, Chi On Chui, Huang-Lin Chao
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Publication number: 20230077541Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.Type: ApplicationFiled: November 8, 2022Publication date: March 16, 2023Inventors: Yasutoshi Okuno, Fu-Ting Yen, Teng-Chun Tsai, Ziwei Fang
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Patent number: 11594633Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.Type: GrantFiled: May 24, 2021Date of Patent: February 28, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Ziwei Fang, Chi On Chui, Huang-Lin Chao
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Publication number: 20230037334Abstract: A semiconductor structure is provided. The semiconductor structure includes an epitaxial structure over a semiconductor substrate. The semiconductor structure also includes a conductive feature over the semiconductor substrate. The conductive feature includes a high-k dielectric layer and a metal layer on the high-k dielectric layer, and a top surface of the metal layer is below a top surface of the high-k dielectric layer. The semiconductor structure further includes a metal-semiconductor compound layer formed on the epitaxial structure. In addition, the semiconductor structure includes a first metal contact structure formed on the top surface of the metal layer of the conductive feature. The semiconductor structure further includes a second metal contact structure formed on the metal-semiconductor compound layer.Type: ApplicationFiled: October 7, 2022Publication date: February 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Liang CHENG, Ziwei FANG
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Patent number: 11563099Abstract: A semiconductor structure is provided. The semiconductor structure includes nanostructures stacked over a substrate and spaced apart from one another, gate dielectric layers wrapping around the nanostructures respectively, nitride layers wrapping around the gate dielectric layers respectively, oxide layers wrapping around the nitride layers respectively, work function layers wrapping around the oxide layers respectively, and a metal fill layer continuously surrounding the work function layers.Type: GrantFiled: August 30, 2021Date of Patent: January 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Liang Cheng, Ziwei Fang
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Patent number: 11532510Abstract: A semiconductor structure includes a metal gate structure disposed over a semiconductor substrate, an interlayer dielectric (ILD) layer disposed over the metal gate structure, and a gate contact disposed in the ILD layer and over the metal gate structure, where a bottom surface of the gate contact is defined by a barrier layer disposed over the metal gate structure, where sidewall surfaces of the gate contact are defined by and directly in contact with the ILD layer, and where the barrier layer is free of nitrogen.Type: GrantFiled: February 15, 2021Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Liang Cheng, Ziwei Fang
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Publication number: 20220384635Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a first dielectric layer, a work function layer, and a gate electrode sequentially stacked over the substrate, the first dielectric layer has a thin portion and a thick portion, the thin portion is thinner than the thick portion and surrounds the thick portion, and the first dielectric layer is a single-layer structure. The semiconductor device structure includes an insulating layer over the substrate and wrapping around the gate stack. The thin portion is between the thick portion and the insulating layer.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Liang CHENG, Ziwei FANG
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Publication number: 20220384439Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a first plurality of stacked semiconductor layers in a p-type transistor region and a second plurality of stacked semiconductor layers in a n-type transistor region. A gate dielectric layer wraps around each of the first and second plurality of stacked semiconductor layers. A first metal gate in the p-type transistor region has a work function metal layer and a first fill metal layer, where the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer is in direct contact with the work function metal layer. A second metal gate in the n-type transistor region has a second fill metal layer that is in direct contact with the gate dielectric layer, where the second fill metal layer has a work function about equal to or lower than 4.3 eV.Type: ApplicationFiled: July 22, 2022Publication date: December 1, 2022Inventors: Mrunal A Khaderbad, Ziwei Fang, Keng-Chu Lin, Hsueh Wen Tsau
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Publication number: 20220376090Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.Type: ApplicationFiled: July 28, 2022Publication date: November 24, 2022Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 11508583Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.Type: GrantFiled: March 16, 2021Date of Patent: November 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yasutoshi Okuno, Teng-Chun Tsai, Ziwei Fang, Fu-Ting Yen
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Patent number: 11501999Abstract: A method for forming a gate structure includes forming a trench within an interlayer dielectric layer (ILD) that is disposed on a semiconductor substrate, the trench exposing a top surface of the semiconductor substrate, forming an interfacial layer at a bottom of the trench, forming a dielectric layer within the trench, forming a work function metal layer on the dielectric layer, forming an in-situ nitride layer on the work function metal layer in the trench, performing a first cobalt deposition process to form a cobalt layer within the trench, performing a second cobalt deposition process to increase a thickness of the cobalt layer within the trench, and performing an electrochemical plating (ECP) process to fill the trench with cobalt.Type: GrantFiled: July 30, 2019Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Liang Cheng, Ziwei Fang
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Publication number: 20220359698Abstract: The present disclosure describes a semiconductor device that includes a substrate and a first transistor on the substrate. The first transistor includes a first gate structure and the first gate structure includes a gate dielectric layer and a first work function layer on the gate dielectric layer. The first gate structure also includes a capping layer on the first work function layer. The semiconductor device also includes a second transistor on the substrate, in which the second transistor includes a second gate structure. The second gate structure includes the gate dielectric layer and a second work function layer on the gate dielectric layer. The second gate structure also includes the first work function layer on the second work function layer and the silicon capping layer on the first work function layer.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Liang CHENG, Peng-Soon Lim, Ziwei Fang, Huang-Lin Chao