Abstract: Embodiments of apparatuses, methods, and systems for providing multiple virtual device controllers by redirecting an interrupt from a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, and virtualization logic. The virtualization logic is to receive a first interrupt from the physical device controller, and in response, send a second interrupt to the processor from one of a plurality of virtual device controllers.

Abstract: An apparatus for secured playback is presented. In one embodiment, the apparatus includes a controller that includes a key derivation module to manage authentication and key derivation. In one embodiment, the apparatus provides a video decryption key to a graphics engine if video data portions in a data stream are retrievable without having to decrypt the data stream. In one embodiment, the apparatus also includes a decryption module to decrypt a part of data in conjunction with an encryption key to generate video information and video data. The controller then writes an encrypted version of the video data to a video buffer of a graphics engine.

Abstract: Apparatuses, methods, and systems for paging instructions for a virtualization engine to local storage. An apparatus includes a processor, a physical device controller, a virtualization engine, system memory, and local storage. The physical device controller is to be shared by a plurality of virtual machines created by a virtual machine monitor installed on a processor. The virtualization engine is to represent the physical device controller as a plurality of virtual device controllers available to be allocated to the plurality of virtual machines. The local storage is separate from the physical memory to store instructions transferred from the system memory for execution by the virtualization engine.

Abstract: An apparatus for secured playback is presented. In one embodiment, the apparatus includes a controller that includes a key derivation module to manage authentication and key derivation. In one embodiment, the apparatus provides a video decryption key to a graphics engine if video data portions in a data stream are retrievable without having to decrypt the data stream. In one embodiment, the apparatus also includes a decryption module to decrypt a part of data in conjunction with an encryption key to generate video information and video data. The controller then writes an encrypted version of the video data to a video buffer of a graphics engine.

Abstract: A method and apparatus for dedicating cache entries to certain streams for performance optimization are disclosed. The method according to the present techniques comprises partitioning a cache array into one or more special-purpose entries and one or more general-purpose entries, wherein special-purpose entries are only allocated for one or more streams having a particular stream ID.

Abstract: Embodiments of apparatuses, methods, and systems for providing multiple virtual device controllers by redirecting an interrupt from a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, and virtualization logic. The virtualization logic is to receive a first interrupt from the physical device controller, and in response, send a second interrupt to the processor from one of a plurality of virtual device controllers.

Abstract: Embodiments of apparatuses, methods, and systems for injecting transactions to support the virtualization of a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, system memory, a physical device controller, and a virtualization agent. The physical device controller is to be shared by a plurality of virtual machines created by a virtual machine monitor installed on a processor. The virtualization agent is coupled to the system memory through a first interface and coupled to the physical device controller through a second interface, to represent the physical device controller as a plurality of virtual device controllers available to be allocated to the plurality of virtual machines, and to inject transactions onto the first interface and the second interface on behalf of the plurality of virtual device controllers.

Abstract: Embodiments of apparatuses, methods, and systems for paging instructions for a virtualization engine to local storage are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, a virtualization engine, system memory, and local storage. The physical device controller is to be shared by a plurality of virtual machines created by a virtual machine monitor installed on a processor. The virtualization engine is to represent the physical device controller as a plurality of virtual device controllers available to be allocated to the plurality of virtual machines. The local storage is separate from the physical memory to store instructions transferred from the system memory for execution by the virtualization engine.

Abstract: Embodiments of apparatuses, methods, and systems for providing multiple virtual device controllers by redirecting an interrupt from a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, and virtualization logic. The virtualization logic is to receive a first interrupt from the physical device controller, and in response, send a second interrupt to the processor from one of a plurality of virtual device controllers.

Abstract: Machine-readable media, methods, and apparatus are described to recover from stream under-run and/or over-run conditions. In some embodiments, an audio controller may discard any partial sample block of the stream.

Abstract: An integrated circuit communicates with memory devices. Data from the memory devices arrives at the integrated circuit with varying propagation delays. The integrated circuit detects the arrival of data from the memory devices, and stores the data in FIFOs. A FIFO drain signal is generated responsive to the detection of the data arrival.

Abstract: For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.

Abstract: Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

Abstract: A prioritized address decoder has been disclosed. One embodiment of the prioritized address decoder includes a first comparator to compare a destination device address of data with a first address range associated with a first device and a second comparator coupled to the first comparator to compare the destination device address with a second address range associated with a second device, wherein the data is sent to the second device in response to a first output of the first comparator and a second output of the second comparator.

Abstract: The invention describes a technology for closing DRAM pages, wherein the invention allows for dynamically changing code streams by tracking the previous decisions made on page closes and adjusts dynamically during DRAM operation to compensate for bad page close decisions made.

Abstract: Machine-readable media, methods, and apparatus are described to recover from stream under-run and/or over-run conditions. In some embodiments, an audio controller may discard any partial sample block of the stream.

Abstract: Embodiments of a memory scoreboard are presented herein. The memory scoreboard tracks memory requests for each rank and bank of memory being addressed. When there are no pending requests, the scoreboard provides an indication to an idle timer that begins a count down to close a current page of the memory. The idle timer can be configured dynamically to close memory pages and to address dynamically-changing code streams by tracking previous decisions made on page closes.

Abstract: A method, apparatus, and system are described. In one embodiment, the method comprises a chipset receiving a plurality of memory requests, wherein each memory request comprises one or more micro-commands that each require one or more memory clock cycles to execute, and scheduling the execution of each of the micro-commands from more than one of the plurality of memory requests in an order to reduce the number of total memory clock cycles required to complete execution of the more than one memory requests.

Abstract: An integrated circuit communicates with memory devices. Data from the memory devices arrives at the integrated circuit with varying propagation delays. The integrated circuit detects the arrival of data from the memory devices, and stores the data in FIFOs. A FIFO drain signal is generated responsive to the detection of the data arrival.

Abstract: A method, apparatus, and system are disclosed. In one embodiment, the method receiving data from a memory on a first interconnect of at least one interconnect, receiving a source-synchronous data strobe from the memory, creating at least a nominal, an early, and a delayed compensated data strobe from the received data strobe, latching the received data with the nominal, early, or delayed compensated data strobe, outputting the latched data onto one or more of the at least one interconnect.