Abstract: For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.

Abstract: Machine-readable media, methods, and apparatus are described to recover from stream under-run and/or over-run conditions. In some embodiments, an audio controller may discard any partial sample block of the stream.

Abstract: The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.

Abstract: Machine-readable media, methods, and apparatus are described to stream data between a codec and a buffer in system memory and to maintain a value in system memory that is indicative of a current position in the buffer. In some embodiments, an audio controller streams the data across an isochronous channel having relaxed ordering rules to the buffer in the system memory and updates the value indicative of current position via a write across the isochronous channel to the system memory.

Abstract: An address translation apparatus and method that can convert a limited-range memory address from a peripheral device to an expanded-range memory address on the fly. The invention can expand the limited address capability of a peripheral bus, such as a PCI bus with a 4 GB address range, to a much larger address capability, such as a 64 GB address range. This conversion can be performed on the fly by hardware, so that no appreciable delay in transfer time is created. The conversion can be performed by adding features to a conventional graphics controller interface, thus minimizing the impact on circuit complexity and system cost.

Abstract: Embodiments of a memory scoreboard are presented herein.

Abstract: Embodiments of dynamic update adaptive idle timer are presented herein.

Abstract: Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

Abstract: A programmable multi-cycle signaling scheme provides synchronous communications over relatively large distances. An input digital data stream is de-multiplexed onto multiple conductors. The digital data stream is recreated at the far end of the conductors.

Abstract: Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

Abstract: In one embodiment, the present invention includes a method for performing an operation in a processor of a uniprocessor system, initiating a write transaction to send a result of the operation to a memory of the uniprocessor system, and issuing a global observation point for the write transaction to the processor before the result is written into the memory. In some embodiments, the global observation point may be issued earlier than if the processor were in a multiprocessor system. Other embodiments are described and claimed.

Abstract: A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of memory devices in a system in response to a second type of reset in the system being initiated if the memory devices are not initialized and enabling a deterministic shutdown mode in a memory controller, which is coupled to the memory devices, after the memory devices have been initialized. Other embodiments are described and claimed.

Abstract: The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.

Abstract: According to one embodiment, computer system is disclosed. The computer system includes a central processing unit (CPU), a bus coupled to the CPU and a chipset coupled to the bus. The chipset includes compensation circuitry to compensate for process, voltage and temperature (PVT) effects attributed to a voltage change on the bus.

Abstract: Embodiments of the present invention provide a method and apparatus for detecting an interruption in memory initialization. A status bit for indicating whether memory initialization was interrupted or not is stored in a register. A basic input/output system (BIOS) sets the status bit prior to initialization and clears the status bit after initialization. The status bit cannot be reset by a standard platform reset. In operation, as the system is reset or turned on and prior to initialization, the BIOS checks the status bit to detect possible improper memory initialization. When the status bit is set, the BIOS concludes that a memory initialization had not completed and thus might be incorrect. The BIOS then causes power to be cycled to memory and any other steps needed are taken to return the memory to a functional state.

Abstract: A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.

Abstract: A method is described that involves, for a first read of information from a memory, activating termination loads on a memory controller's side of a data bus between a memory controller and a memory. The method also involves, for a write of information into the memory, deactivating the termination loads. The method also involves, for a second read of information from the memory, activating the termination loads.

Abstract: A method and apparatus for delivering APIC interrupts to a processor, and between processors, as FSB transactions. Interrupts and hardware signals, generated by a PCI device, are converted into an upstream memory write interrupt and further converted into an FSB interrupt transaction, received by a processor. Interrupts marked as lowest priority re-directable are redirected based on task priority information. Support for XTPR transactions to update XTPR registers is provided. Preferred ordering of XTPR update transactions and interrupts to be redirected is provided.

Abstract: An apparatus and method for prefetching cache data in response to data requests. The prefetching uses the memory addresses of requested data to search for other data, from a related address, in a cache. This, or other data, may then be prefetched based on the result of the search.

Abstract: An integrated circuit designed to be coupled to a suspendable memory, the integrated circuit comprising a memory enable deassertion delay (MEDD) logic setting a wait period for the deassertion of a memory enable signal after completion of a memory operation. The wait period is chosen for a preferred latency versus power savings tradeoff.