Patents by Inventor Zongrong Liu

Zongrong Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210057242
    Abstract: A piece of pick and place tool or a chip bonding equipment, which has innovative designs enabling chip(s) on a tape to get picked up without touching its front surface, is invented. The designs use levitation technologies to receive and hold the chips detached from the tape from a face-down position. A streamline design is also invented to provide better productivity. The invented pick and place tool or chip bonder is particularly useful for applications which require using chips with zero tolerance of particle and/or contamination on the chip front surfaces.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: Yunjun Tang, Zongrong Liu, Ge Yi
  • Publication number: 20210005572
    Abstract: A piece of chip-to-wafer and chip-to-chip bonding equipment, which has innovative designs enabling chip(s) from either a diamagnetic carrier or a diced wafer to expose the chip back side surface for pickup, is invented. The designs either use a levitation technology, or air dynamic, or a novel mechanical design to fulfill the chip front surfaces touchless requirement to avoid the chip surface contamination. The invented chip bonder is particularly useful for bonding applications which require using chips with zero tolerance of particle and/or contamination on the chip front surfaces or bonding surfaces.
    Type: Application
    Filed: July 7, 2019
    Publication date: January 7, 2021
    Inventors: Dong Li, Ying Ma, Ge Yi, Zongrong Liu
  • Publication number: 20200382092
    Abstract: An acoustic wave device system with its piezoelectric layer originating from a single crystal piezoelectric wafer/substrate is invented along with sets of detailed process steps to fabricate such a device using wafer-to-wafer and/or die-to-wafer bonding technologies. The proposed device system is particularly good to make bulk acoustic wave (BAW) devices. Methods allowing the single crystal piezoelectric wafer/substrate to be re-used are also given. The proposed methods include detailed process steps to allow heterogeneous integration of electrical chips into the system in a very cost efficient manner. The invention provides a practical and low-cost approach to fabricate the radio frequency (RF) front end chip incorporating RF filters and electronic components integrated into a small footprint which is particularly useful for mobile device and RF stations.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 3, 2020
    Inventors: Dong Li, Ying Ma, Ge Yi, Zongrong Liu
  • Patent number: 10641966
    Abstract: A free space coupling system comprising a waveguide horizontally positioned on an integrated circuit, and a silicon housing coupled to the waveguide, wherein the silicon housing comprises a reflective surface, a first port, wherein the first port is configured to receive light from an optic source positioned substantially parallel to the waveguide at a coupling point, and a second port, wherein the second port is oriented at about ninety degrees with respect to the first port, and wherein the second port is aligned with a grating port on the waveguide.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: May 5, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventors: Rongsheng Miao, Zongrong Liu, Qianfan Xu, Xiao Shen
  • Patent number: 10539744
    Abstract: A gapless optical mode converter comprising a fiber holder configured to receive and hold an optical transmission line, a first glass block coupled via an optical adhesive at a first side to the fiber holder, a lens coupled via the optical adhesive at a first side to a second side of the first glass block, and a holder configured to hold the fiber holder, the first glass block, and the lens.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: January 21, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventors: Rongsheng Miao, Zongrong Liu, Xueyan Zheng, Xiao Shen
  • Patent number: 10197733
    Abstract: An edge coupling device including a substrate, a buried oxide disposed over the substrate, a cladding material disposed over the buried oxide, where the cladding material includes a trench, an inversely tapered silicon waveguide disposed within the cladding material beneath the trench, and a ridge waveguide disposed within the trench, where the ridge waveguide and the inversely tapered silicon waveguide are vertically-aligned with each other.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: February 5, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Huapu Pan, Zongrong Liu, Hongzhen Wei, Hongmin Chen
  • Patent number: 9933570
    Abstract: A method for fabricating a photonic integrated circuit (PIC) comprises providing a wafer comprising an insulator layer positioned between a top semiconductor layer and a base semiconductor layer, patterning the top semiconductor layer to simultaneously define a waveguide and a first etch mask window for forming a fiber-guiding v-groove that substantially aligns to an axis of optical signal propagation of the waveguide, removing a first portion of the top semiconductor layer to form the waveguide according to the patterning, removing a second portion of the top semiconductor layer to form the first etch mask window according to the patterning, and forming the fiber-guiding v-groove according to the first etch mask window.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: April 3, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Zongrong Liu, Qianfan Xu, Rongsheng Miao, Hongmin Chen, Xiao Shen, Yu Sheng Bai
  • Publication number: 20170254954
    Abstract: A method for fabricating a photonic integrated circuit (PIC) comprises providing a wafer comprising an insulator layer positioned between a top semiconductor layer and a base semiconductor layer, patterning the top semiconductor layer to simultaneously define a waveguide and a first etch mask window for forming a fiber-guiding v-groove that substantially aligns to an axis of optical signal propagation of the waveguide, removing a first portion of the top semiconductor layer to form the waveguide according to the patterning, removing a second portion of the top semiconductor layer to form the first etch mask window according to the patterning, and forming the fiber-guiding v-groove according to the first etch mask window.
    Type: Application
    Filed: March 1, 2016
    Publication date: September 7, 2017
    Inventors: Zongrong Liu, Qianfan Xu, Rongsheng Miao, Hongmin Chen, Xiao Shen, Yu Sheng Bai
  • Publication number: 20170219777
    Abstract: An edge coupling device including a substrate, a buried oxide disposed over the substrate, a cladding material disposed over the buried oxide, where the cladding material includes a trench, an inversely tapered silicon waveguide disposed within the cladding material beneath the trench, and a ridge waveguide disposed within the trench, where the ridge waveguide and the inversely tapered silicon waveguide are vertically-aligned with each other.
    Type: Application
    Filed: April 19, 2017
    Publication date: August 3, 2017
    Inventors: Huapu Pan, Zongrong Liu, Hongzhen Wei, Hongmin Chen
  • Publication number: 20170205582
    Abstract: A gapless optical mode converter comprising a fiber holder configured to receive and hold an optical transmission line, a first glass block coupled via an optical adhesive at a first side to the fiber holder, a lens coupled via the optical adhesive at a first side to a second side of the first glass block, and a holder configured to hold the fiber holder, the first glass block, and the lens.
    Type: Application
    Filed: January 11, 2017
    Publication date: July 20, 2017
    Inventors: Rongsheng Miao, Zongrong Liu, Xueyan Zheng, Xiao Shen
  • Patent number: 9703039
    Abstract: A method of fabricating an edge coupling device and an edge coupling device are provided. The method includes removing a portion of cladding material to form a trench over an inversely tapered silicon waveguide, depositing a material having a refractive index greater than silicon dioxide over remaining portions of the cladding material and in the trench, and removing a portion of the material within the trench to form a ridge waveguide.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: July 11, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventors: Huapu Pan, Zongrong Liu, Hongzhen Wei, Hongmin Chen
  • Publication number: 20170192175
    Abstract: A free space coupling system comprising a waveguide horizontally positioned on an integrated circuit, and a silicon housing coupled to the waveguide, wherein the silicon housing comprises a reflective surface, a first port, wherein the first port is configured to receive light from an optic source positioned substantially parallel to the waveguide at a coupling point, and a second port, wherein the second port is oriented at about ninety degrees with respect to the first port, and wherein the second port is aligned with a grating port on the waveguide.
    Type: Application
    Filed: March 20, 2017
    Publication date: July 6, 2017
    Inventors: Rongsheng Miao, Zongrong Liu, Qianfan Xu, Xiao Shen
  • Patent number: 9672847
    Abstract: Micrometer scale components comprise a component body comprising an alloy of a first solder metal and a second solder metal, the alloy having a higher liquidus temperature than the second solder metal; and a base region of the structure body wetted to a substrate, wherein the component body has a molded surface profile.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: June 6, 2017
    Assignee: Western Digital (Fremont), LLC
    Inventors: Zongrong Liu, Lei Wang
  • Patent number: 9632281
    Abstract: A free space coupling system comprising a waveguide horizontally positioned on an integrated circuit, and a silicon housing coupled to the waveguide, wherein the silicon housing comprises a reflective surface, a first port, wherein the first port is configured to receive light from an optic source positioned substantially parallel to the waveguide at a coupling point, and a second port, wherein the second port is oriented at about ninety degrees with respect to the first port, and wherein the second port is aligned with a grating port on the waveguide.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: April 25, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventors: Rongsheng Miao, Zongrong Liu, Qianfan Xu, Xiao Shen
  • Patent number: 9577408
    Abstract: A monolithically integrated thermal tunable laser comprising a layered substrate comprising an upper surface and a lower surface, and a thermal tuning assembly comprising a heating element positioned on the upper surface, a waveguide layer positioned between the upper surface and the lower surface, and a thermal insulation layer positioned between the waveguide layer and the lower surface, wherein the thermal insulation layer is at least partially etched out of an Indium Phosphide (InP) sacrificial layer, and wherein the thermal insulation layer is positioned between Indium Gallium Arsenide (InGaAs) etch stop layers.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: February 21, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventors: Hongmin Chen, Xuejin Yan, Rongsheng Miao, Xiao Shen, Zongrong Liu
  • Publication number: 20160118772
    Abstract: A monolithically integrated thermal tunable laser comprising a layered substrate comprising an upper surface and a lower surface, and a thermal tuning assembly comprising a heating element positioned on the upper surface, a waveguide layer positioned between the upper surface and the lower surface, and a thermal insulation layer positioned between the waveguide layer and the lower surface, wherein the thermal insulation layer is at least partially etched out of an Indium Phosphide (InP) sacrificial layer, and wherein the thermal insulation layer is positioned between Indium Gallium Arsenide (InGaAs) etch stop layers.
    Type: Application
    Filed: December 31, 2015
    Publication date: April 28, 2016
    Applicant: Futurewei Technologies, Inc.
    Inventors: Hongmin CHEN, Xuejin YAN, Rongsheng MIAO, Xiao SHEN, Zongrong LIU
  • Patent number: 9293694
    Abstract: A new class of the memory cell is proposed. There are two separated pulse data writing and sensing current paths. The in-plane pulse current is used to flip the magnetization direction of the perpendicular-anisotropy data storage layer sandwiched between a heavy metal writing current-carrying layer and a dielectric layer. The magnetization state within data storage layer is detected by the patterned perpendicular-anisotropy tunneling magnetoresistive (TMR) stack via the output potential of the stack.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: March 22, 2016
    Inventors: Ge Yi, Shaoping Li, Dong Li, Yunjun Tang, Zongrong Liu
  • Publication number: 20160005427
    Abstract: Micrometer scale components comprise a component body comprising an alloy of a first solder metal and a second solder metal, the alloy having a higher liquidus temperature than the second solder metal; and a base region of the structure body wetted to a substrate, wherein the component body has a molded surface profile.
    Type: Application
    Filed: September 14, 2015
    Publication date: January 7, 2016
    Inventors: ZONGRONG LIU, LEI WANG
  • Patent number: 9231361
    Abstract: A monolithically integrated thermal tunable laser comprising a layered substrate comprising an upper surface and a lower surface, and a thermal tuning assembly comprising a heating element positioned on the upper surface, a waveguide layer positioned between the upper surface and the lower surface, and a thermal insulation layer positioned between the waveguide layer and the lower surface, wherein the thermal insulation layer is at least partially etched out of an Indium Phosphide (InP) sacrificial layer, and wherein the thermal insulation layer is positioned between Indium Gallium Arsenide (InGaAs) etch stop layers.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: January 5, 2016
    Assignee: Futurewei Technologies, Inc.
    Inventors: Hongmin Chen, Xuejin Yan, Rongsheng Miao, Xiao Shen, Zongrong Liu
  • Publication number: 20150293303
    Abstract: A method of fabricating an edge coupling device and an edge coupling device are provided. The method includes removing a portion of cladding material to form a trench over an inversely tapered silicon waveguide, depositing a material having a refractive index greater than silicon dioxide over remaining portions of the cladding material and in the trench, and removing a portion of the material within the trench to form a ridge waveguide.
    Type: Application
    Filed: April 7, 2015
    Publication date: October 15, 2015
    Inventors: Huapu Pan, Zongrong Liu, Hongzhen Wei, Hongmin Chen