Patents by Inventor Zongrong Liu

Zongrong Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150293303
    Abstract: A method of fabricating an edge coupling device and an edge coupling device are provided. The method includes removing a portion of cladding material to form a trench over an inversely tapered silicon waveguide, depositing a material having a refractive index greater than silicon dioxide over remaining portions of the cladding material and in the trench, and removing a portion of the material within the trench to form a ridge waveguide.
    Type: Application
    Filed: April 7, 2015
    Publication date: October 15, 2015
    Inventors: Huapu Pan, Zongrong Liu, Hongzhen Wei, Hongmin Chen
  • Patent number: 9159345
    Abstract: Micrometer scale components comprise a component body comprising an alloy of a first solder metal and a second solder metal, the alloy having a higher liquidus temperature than the second solder metal; and a base region of the structure body wetted to a substrate, wherein the component body has a molded surface profile.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: October 13, 2015
    Assignee: Western Digital (Fremont), LLC
    Inventors: Zongrong Liu, Lei Wang
  • Publication number: 20150260931
    Abstract: A free space coupling system comprising a waveguide horizontally positioned on an integrated circuit, and a silicon housing coupled to the waveguide, wherein the silicon housing comprises a reflective surface, a first port, wherein the first port is configured to receive light from an optic source positioned substantially parallel to the waveguide at a coupling point, and a second port, wherein the second port is oriented at about ninety degrees with respect to the first port, and wherein the second port is aligned with a grating port on the waveguide.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 17, 2015
    Applicant: Futurewei Technologies, Inc.
    Inventors: Rongsheng Miao, Zongrong Liu, Qianfan Xu, Xiao Shen
  • Patent number: 9012265
    Abstract: A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: April 21, 2015
    Inventors: Ge Yi, Zongrong Liu, Yunjun Tang, Shaoping Li
  • Patent number: 8997832
    Abstract: A method for manufacturing micrometer scale components comprises depositing a first metal on a substrate, depositing a second metal in a mold, and alloying the first and second metals together to form the component.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: April 7, 2015
    Assignee: Western Digital (Fremont), LLC
    Inventors: Zongrong Liu, Lei Wang
  • Publication number: 20140321488
    Abstract: A monolithically integrated thermal tunable laser comprising a layered substrate comprising an upper surface and a lower surface, and a thermal tuning assembly comprising a heating element positioned on the upper surface, a waveguide layer positioned between the upper surface and the lower surface, and a thermal insulation layer positioned between the waveguide layer and the lower surface, wherein the thermal insulation layer is at least partially etched out of an Indium Phosphide (InP) sacrificial layer, and wherein the thermal insulation layer is positioned between Indium Gallium Arsenide (InGaAs) etch stop layers.
    Type: Application
    Filed: April 30, 2014
    Publication date: October 30, 2014
    Applicant: Futurewei Technologies, Inc.
    Inventors: Hongmin Chen, Xuejin Yan, Rongshen Miao, Xiao Shen, Zongrong Liu
  • Patent number: 8860216
    Abstract: A method and system for providing a laser diode submount for use in an energy assisted magnetic recording disk drive are described. A portion of a silicon substrate is removed, forming trenches therein. Each trench has sidewalls, surrounds a silicon island corresponding to a laser diode submount, and corresponds to a thickness of the laser diode submount. The silicon island has a top surface and a facets corresponding to the trench sidewalls. Insulator(s) for the top surface and facets of the silicon island are provided. Metallization is provided on the top surface and facets of the silicon island. A first portion of the metallization on the top surface corresponds to under bump metal (UBM) for solder pad(s). A second portion of the metallization corresponds to electrical traces. Solder pad(s) are provided on the UBM. The silicon island is released from the silicon substrate.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: October 14, 2014
    Assignee: Western Digital (Fremont), LLC
    Inventors: Lei Wang, Zongrong Liu, Pezhman Monadgemi
  • Publication number: 20130307097
    Abstract: A magnetic memory cell comprises in-plane anisotropy tunneling magnetic junction (TMJ) and two fixed in-plane storage-stabilized layers, which splits on the both side of the data storage layer of the TMJ. The magnetizations of the said fixed in-plane storage-stabilized layers are all normal to that of the reference layer of TMJ but point to opposite direction. The existing of the storage-stabilized layers not only enhances the stability of the data storage, but also can reduce the critical current needed to flip the data storage layer via some specially added features.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 21, 2013
    Inventors: Ge Yi, Shaoping Li, Yunjun Tang, Zongrong Liu, Dujiang Wan
  • Publication number: 20130270661
    Abstract: A new magnetic memory cell comprises a perpendicular-anisotropy tunneling magnetic junction (TMJ) and a fixed in-plane spin-polarizing layer, which is separated from the perpendicular-anisotropy data storage layer of tunneling magnetic junction by a non-magnetic layer. The non-magnetic layer can be made of metallic or dielectric materials.
    Type: Application
    Filed: April 16, 2012
    Publication date: October 17, 2013
    Inventors: Ge Yi, Shaoping Li, Yunjun Tang, Zongrong Liu
  • Publication number: 20130252375
    Abstract: A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose.
    Type: Application
    Filed: March 26, 2012
    Publication date: September 26, 2013
    Inventors: Ge Yi, Zongrong Liu, Yunjun Tang, Shaoping Li
  • Patent number: 8518748
    Abstract: A method and system for providing a laser diode submount for use in an energy assisted magnetic recording disk drive are described. A portion of a silicon substrate is removed, forming trenches therein. Each trench has sidewalls, surrounds a silicon island corresponding to a laser diode submount, and corresponds to a thickness of the laser diode submount. The silicon island has a top surface and a facets corresponding to the trench sidewalls. Insulator(s) for the top surface and facets of the silicon island are provided. Metallization is provided on the top surface and facets of the silicon island. A first portion of the metallization on the top surface corresponds to under bump metal (UBM) for solder pad(s). A second portion of the metallization corresponds to electrical traces. Solder pad(s) are provided on the UBM. The silicon island is released from the silicon substrate.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: August 27, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Lei Wang, Zongrong Liu, Pezhman Monadgemi
  • Publication number: 20130114334
    Abstract: A new class of the memory cell is proposed. There are two separated pulse data writing and sensing current paths. The in-plane pulse current is used to flip the magnetization direction of the perpendicular-anisotropy data storage layer sandwiched between a heavy metal writing current-carrying layer and a dielectric layer. The magnetization state within data storage layer is detected by the patterned perpendicular-anisotropy tunneling magnetoresistive (TMR) stack via the output potential of the stack.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 9, 2013
    Inventors: Ge Yi, Shaoping Li, Dong Li, Yunjun Tang, Zongrong Liu
  • Patent number: 8324081
    Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: December 4, 2012
    Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, Jr., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu
  • Patent number: 8288204
    Abstract: Methods for fabricating components with precise dimension control are described. One such method includes providing a workpiece including a top layer and a bottom layer of silicon separated by a layer of SiOx, where each of the three layers has about the same length and width, removing edge portions of the top layer, thereby exposing portions of the SiOx layer, etching the exposed portions of the SiOx layer and portions of the SiOx layer disposed between the top layer and bottom layer, thereby forming undercut sections between the top layer and bottom layer, growing a second layer of SiOx having a preselected thickness on the workpiece, depositing metal on the workpiece such that the metal deposited on the top layer is not continuous with the metal deposited on the bottom layer, and removing the bottom layer and a portion of the SiOx layer having a preselected thickness.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: October 16, 2012
    Assignee: Western Digital (Fremont), LLC
    Inventors: Lei Wang, Zongrong Liu
  • Publication number: 20110147943
    Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).
    Type: Application
    Filed: March 4, 2011
    Publication date: June 23, 2011
    Applicant: Vertical Circuits, Inc.
    Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, JR., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu
  • Patent number: 7923349
    Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: April 12, 2011
    Assignee: Vertical Circuits, Inc.
    Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, Jr., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu
  • Publication number: 20080315434
    Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).
    Type: Application
    Filed: June 19, 2008
    Publication date: December 25, 2008
    Applicant: Vertical Circuits, Inc.
    Inventors: Simon J.S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, JR., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu