Patents by Inventor Zubin HUANG
Zubin HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230002894Abstract: A method and apparatus for processing a substrate are described herein. The methods and apparatus described enable the raising and lowering of a shadow ring within a process chamber either simultaneously with or separately from a plurality of substrate lift pins. The shadow ring is raised and lowered using a shadow ring lift assembly and may be raised to a pre-determined height above the substrate during a radical treatment operation. The shadow ring lift assembly may also raise and lower the plurality of substrate lift pins to enable both the shadow ring and the substrate lift pins to be raised to a transfer position when the substrate is being transferred into or out of the process chamber.Type: ApplicationFiled: September 13, 2021Publication date: January 5, 2023Inventors: Zubin HUANG, Jallepally Ravi, Kai WU, Xiaoxiong YUAN
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Patent number: 11532525Abstract: Methods and systems for controlling concentration profiles of deposited films using machine learning are provided. Data associated with a target concentration profile for a film to be deposited on a surface of a substrate during a deposition process for the substrate is provided as input to a trained machine learning model. One or more outputs of the trained machine learning model are obtained. Process recipe data identifying one or more sets of deposition process settings is determined from the one or more outputs. For each set of deposition process setting, an indication of a level of confidence that a respective set of deposition process settings corresponds to the target concentration profile for the film to be deposited on the substrate is also determined.Type: GrantFiled: March 3, 2021Date of Patent: December 20, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Anton V Baryshnikov, Aykut Aydin, Zubin Huang, Rui Cheng, Yi Yang, Diwakar Kedlaya, Venkatanarayana Shankaramurthy, Krishna Nittala, Karthik Janakiraman
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Patent number: 11527408Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.Type: GrantFiled: May 5, 2020Date of Patent: December 13, 2022Assignee: Applied Materials, Inc.Inventors: Tzu-shun Yang, Rui Cheng, Karthik Janakiraman, Zubin Huang, Diwakar Kedlaya, Meenakshi Gupta, Srinivas Guggilla, Yung-chen Lin, Hidetaka Oshio, Chao Li, Gene Lee
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Patent number: 11456173Abstract: Embodiments for processing a substrate are provided and include a method of trimming photoresist to provide photoresist profiles with smooth sidewall surfaces and to tune critical dimensions (CD) for the patterned features and/or a subsequently deposited dielectric layer. The method can include depositing a sacrificial structure layer on the substrate, depositing a photoresist on the sacrificial structure layer, and patterning the photoresist to produce a crude photoresist profile on the sacrificial structure layer. The method also includes trimming the photoresist with a plasma to produce a refined photoresist profile covering a first portion of the sacrificial structure layer while a second portion of the sacrificial structure layer is exposed, etching the second portion of the sacrificial structure layer to form patterned features disposed on the substrate, and depositing a dielectric layer on the patterned features.Type: GrantFiled: February 21, 2020Date of Patent: September 27, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Meenakshi Gupta, Rui Cheng, Srinivas Guggilla, Karthik Janakiraman, Diwakar N. Kedlaya, Zubin Huang
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Publication number: 20220285232Abstract: Methods and systems for controlling concentration profiles of deposited films using machine learning are provided. Data associated with a target concentration profile for a film to be deposited on a surface of a substrate during a deposition process for the substrate is provided as input to a trained machine learning model. One or more outputs of the trained machine learning model are obtained. Process recipe data identifying one or more sets of deposition process settings is determined from the one or more outputs. For each set of deposition process setting, an indication of a level of confidence that a respective set of deposition process settings corresponds to the target concentration profile for the film to be deposited on the substrate is also determined.Type: ApplicationFiled: March 3, 2021Publication date: September 8, 2022Inventors: Anton V. Baryshnikov, Aykut Aydin, Zubin Huang, Rui Cheng, Yi Yang, Diwakar Kedlaya, Venkatanarayana Shankaramurthy, Krishna Nittala, Karthik Janakiraman
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Publication number: 20220199373Abstract: Exemplary semiconductor processing chambers include a chamber body defining a processing region. The chambers may include a substrate support disposed within the processing region. The substrate support may have an upper surface that defines a recessed substrate seat. The chambers may include a shadow ring disposed above the substrate seat and the upper surface. The shadow ring may extend about a peripheral edge of the substrate seat. The chambers may include bevel purge openings defined within the substrate support proximate the peripheral edge. A bottom surface of the shadow ring may be spaced apart from a top surface of the upper surface to form a purge gas flow path that extends from the bevel purge openings along the shadow ring. A space formed between the shadow ring and the substrate seat may define a process gas flow path. The gas flow paths may be in fluid communication with one another.Type: ApplicationFiled: December 18, 2020Publication date: June 23, 2022Applicant: Applied Materials, Inc.Inventors: Venkata Sharat Chandra Parimi, Zubin Huang, Manjunath Veerappa Chobari Patil, Nitin Pathak, Yi Yang, Badri N. Ramamurthi, Truong Van Nguyen, Rui Cheng, Diwakar Kedlaya
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Patent number: 11315787Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.Type: GrantFiled: March 17, 2020Date of Patent: April 26, 2022Assignee: Applied Materials, Inc.Inventors: Tzu-shun Yang, Rui Cheng, Karthik Janakiraman, Zubin Huang, Diwakar Kedlaya, Meenakshi Gupta, Srinivas Guggilla, Yung-chen Lin, Hidetaka Oshio, Chao Li, Gene Lee
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Publication number: 20220108892Abstract: Embodiments of the present technology include semiconductor processing methods to make boron-and-silicon-containing layers that have a changing atomic ratio of boron-to-silicon. The methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber, and also flowing a boron-containing precursor and molecular hydrogen (H2) into the substrate processing region of the semiconductor processing chamber. The boron-containing precursor and the H2 may be flowed at a boron-to-hydrogen flow rate ratio. The flow rate of the boron-containing precursor and the H2 may be increased while the boron-to-hydrogen flow rate ratio remains constant during the flow rate increase. The boron-and-silicon-containing layer may be deposited on a substrate, and may be characterized by a continuously increasing ratio of boron-to-silicon from a first surface in contact with the substrate to a second surface of the boron-and-silicon-containing layer furthest from the substrate.Type: ApplicationFiled: October 5, 2020Publication date: April 7, 2022Applicant: Applied Materials, Inc.Inventors: Yi Yang, Krishna Nittala, Rui Cheng, Karthik Janakiraman, Diwakar Kedlaya, Zubin Huang, Aykut Aydin
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Publication number: 20220108891Abstract: Exemplary semiconductor processing chambers may include a faceplate assembly characterized by at least one surface defining a number of voids. Each void is configured to receive an interchangeable thermal body that can be selected from multiple interchangeable thermal bodies. Exemplary semiconductor processing chambers may also include a gas box characterized by movable members. Each movable member is configured to engage a delivery port and is movable to provide flow control for a gas being delivered to the processing volume through a gas flow path. Zoned flow and/or temperature control may be provided by the faceplate assembly, the gas box, or both.Type: ApplicationFiled: October 6, 2020Publication date: April 7, 2022Applicant: Applied Materials, Inc.Inventors: Zubin Huang, Manjunath Veerappa Chobari Patil, Diwakar Kedlaya, Truong Van Nguyen, Pavan Kumar Murali Kumar, Subrahmanyam Veerisetty, Venkata Sharat Chandra Parimi, Fang Ruan
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Publication number: 20220108872Abstract: Exemplary semiconductor processing systems may include a chamber body comprising sidewalls and a base. The systems may include a substrate support extending through the base of the chamber body. The substrate support may include a support plate defining a plurality of channels through an interior of the support plate. Each channel of the plurality of channels may include a radial portion extending outward from a central channel through the support plate. Each channel may also include a vertical portion formed at an exterior region of the support plate fluidly coupling the radial portion with a support surface of the support plate. The substrate support may include a shaft coupled with the support plate. The central channel may extend through the shaft. The systems may include a fluid source coupled with the central channel of the substrate support.Type: ApplicationFiled: October 5, 2020Publication date: April 7, 2022Applicant: Applied Materials, Inc.Inventors: Zubin Huang, Diwakar Kedlaya, Rui Cheng, Truong Van Nguyen, Manjunath Patil, Pavan Kumar Murali Kumar, Subrahmanyam Veerisetty, Karthik Janakiraman
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Publication number: 20220093371Abstract: Exemplary semiconductor processing systems include a chamber body having sidewalls and a base. The systems may include a substrate support extending through the base. The substrate support may include a support plate defining lift pin locations and a shaft coupled with the support plate. The systems may include a shield coupled with the shaft and extending below the support plate. The shield may define a central aperture that extends beyond an outer periphery of the shaft. The systems may include a purge baffle coupled with the shield at a position that is beyond the central aperture such that a space between the purge baffle and the shaft is in fluid communication with a space between the shield and the support plate. The purge baffle may extend along at least a portion of the shaft. The systems may include a purge gas source coupled with the purge baffle.Type: ApplicationFiled: September 21, 2020Publication date: March 24, 2022Applicant: Applied Materials, Inc.Inventors: Zubin Huang, Truong Van Nguyen, Rui Cheng, Diwakar Kedlaya, Manjunath Veerappa Chobari Patil, Prashant A. Desai, Paul L. Brillhart, Karthik Janakiraman, Pavan Kumar Murali Kumar
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Publication number: 20220020583Abstract: Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region, and the substrate may be maintained at a temperature below or about 450° C. The methods may include striking a plasma of the silicon-containing precursor. The methods may include forming a layer of amorphous silicon on a semiconductor substrate. The layer of amorphous silicon may be characterized by less than or about 3% hydrogen incorporation.Type: ApplicationFiled: July 19, 2020Publication date: January 20, 2022Applicant: Applied Materials, Inc.Inventors: Rui Cheng, Diwakar Kedlaya, Karthik Janakiraman, Gautam K. Hemani, Krishna Nittala, Alicia J. Lustgraaf, Zubin Huang, Brett Spaulding, Shashank Sharma, Kelvin Chan
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Publication number: 20210320027Abstract: Exemplary methods of semiconductor processing may include coupling a fluid conduit within a substrate support in a semiconductor processing chamber to a system foreline. The coupling may vacuum chuck a substrate with the substrate support. The methods may include flowing a gas into the fluid conduit. The methods may include maintaining a pressure between the substrate and the substrate support at a pressure higher than the pressure at the system foreline.Type: ApplicationFiled: April 9, 2020Publication date: October 14, 2021Applicant: Applied Materials, Inc.Inventors: Zubin Huang, Rui Cheng, Diwakar Kedlaya, Satish Radhakrishnan, Anton V. Baryshnikov, Venkatanarayana Shankaramurthy, Karthik Janakiraman, Paul L. Brillhart, Badri N. Ramamurthi
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Publication number: 20210183657Abstract: Methods and apparatus for surface profiling and texturing of chamber components for use in a process chamber, such surface-profiled or textured chamber components, and method of use of same are provided herein. In some embodiments, a method includes measuring a parameter of a reference substrate or a heated pedestal using one or more sensors and modifying a surface of a chamber component based on the measured parameter.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Inventors: DAVID W. GROECHEL, MICHAEL R. RICE, GANG GRANT PENG, RUI CHENG, ZUBIN HUANG, HAN WANG, KARTHIK JANAKIRAMAN, DIWAKAR KEDLAYA, PAUL L. BRILLHART
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Publication number: 20210147981Abstract: In one aspect, an apparatus includes a chamber body, a blocker plate for delivering process gases into a gas mixing volume, and a face plate having holes through which the mixed gas is distributed to a substrate. In another aspect, the face plate may include a first region with a recess relative to a second region. In another aspect, the blocker plate may include a plurality of regions, each region having different hole patterns/geometries and/or flow profiles. In another aspect, the apparatus may include a radiation shield disposed below a bottom of the substrate support. A shaft or stem of the substrate support includes holes at an upper end thereof near the substrate support.Type: ApplicationFiled: August 10, 2018Publication date: May 20, 2021Inventors: Rui CHENG, Karthik JANAKIRAMAN, Zubin HUANG
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Patent number: 11009455Abstract: Systems and methods used to deliver a processing gas having a desired diborane concentration to a processing volume of a processing chamber are provided herein. In one embodiment a system includes a borane concentration sensor. The borane concentration sensor includes a body and a plurality of windows. Here, individual ones of the plurality of windows are disposed at opposite ends of the body and the body and the plurality of windows collectively define a cell volume. The borane concentration sensor further includes a radiation source disposed outside of the cell volume proximate to a first window of the plurality of windows, and a radiation detector disposed outside the cell volume proximate to a second window of the plurality of windows.Type: GrantFiled: July 2, 2019Date of Patent: May 18, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Zubin Huang, Sarah Langlois White, Jonathan Robert Bakke, Diwakar N. Kedlaya, Juan Carlos Rocha, Fang Ruan
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Publication number: 20210143029Abstract: A system may include a main line for delivering a first gas, and a sensor for measuring a concentration of a precursor in the first gas delivered through the main line. The system may further include first and second sublines for providing fluid access to first and second processing chambers, respectively. The first subline may include a first flow controller for controlling the first gas flowed through the first subline. The second subline may include a second flow controller for controlling the first gas flowed through the second subline. A delivery controller may be configured to control the first and second flow controllers based on the measured concentration of the precursor to deliver a first mixture of the first gas and a second gas and a second mixture of the first and second gases into the first and second semiconductor processing chambers, respectively.Type: ApplicationFiled: November 11, 2020Publication date: May 13, 2021Applicant: Applied Materials, Inc.Inventors: Diwakar Kedlaya, Fang Ruan, Zubin Huang, Ganesh Balasubramanian, Kaushik Alayavalli, Martin Seamons, Kwangduk Lee, Rajaram Narayanan, Karthik Janakiraman
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Publication number: 20210130960Abstract: Exemplary temperature modulation methods may include delivering a gas through a purge line extending within a substrate support. The gas may be directed to a backside surface of the substrate support opposite a substrate support surface. The purge line may extend along a central axis of a shaft, the shaft being hermetically sealed with the substrate support. The substrate support may be characterized by a center and a circumferential edge. A first end of the purge line may be fixed at a first distance from the backside surface of the substrate support. The methods may include flowing the gas at a first flow rate via a flow pathway to remove heat from the substrate support to achieve a desired substrate support temperature profile.Type: ApplicationFiled: October 30, 2020Publication date: May 6, 2021Applicant: Applied Materials, Inc.Inventors: Zubin Huang, Rui Cheng, Jian Li
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Publication number: 20210040617Abstract: Method for depositing amorphous silicon materials are provide and include generating a plasma within a plasma unit in fluid communication with a process chamber and flowing the plasma through an ion suppressor to produce an activated fluid containing reactive species and neutral species. The activated fluid either contains no ions or contains a lower concentration of ions than the plasma. The method further includes flowing the activated fluid into a first inlet of a dual channel showerhead within the process chamber and flowing a silicon precursor into a second inlet of the dual channel showerhead. Thereafter, the method includes flowing a mixture of the activated fluid and the silicon precursor out of the dual channel showerhead and forming an amorphous silicon layer on a substrate disposed in the process chamber.Type: ApplicationFiled: March 13, 2019Publication date: February 11, 2021Inventors: Zubin HUANG, Rui CHENG, Chen-An CHEN, Karthik JANAKIRAMAN
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Publication number: 20200335338Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.Type: ApplicationFiled: March 17, 2020Publication date: October 22, 2020Inventors: Tzu-Shun YANG, Rui CHENG, Karthik JANAKIRAMAN, Zubin HUANG, Diwakar KADLAYA, Meenakshi GUPTA, Srinivas GUGGILLA, Yung-chen LIN, Hidetaka OSHIO, Chao LI, Gene LEE