Patents by Inventor Zulhazmi Mokhti

Zulhazmi Mokhti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11757013
    Abstract: Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a drain finger extending on the semiconductor structure in a first direction, and a drain interconnect extending in the first direction and configured to be coupled to a drain signal at an interior position of the drain interconnect, where the drain interconnect is connected to the drain finger at a position offset from the interior position of the drain interconnect.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: September 12, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Frank Trang, Zulhazmi Mokhti, Haedong Jang
  • Patent number: 11742304
    Abstract: A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: August 29, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Frank Trang, Qianli Mu, Haedong Jang, Zulhazmi Mokhti
  • Patent number: 11652449
    Abstract: Gallium nitride based RF transistor amplifiers include a semiconductor structure having a gallium nitride based channel layer and a gallium nitride based barrier layer thereon, and are configured to operate at a specific direct current drain-to-source bias voltage. These amplifiers are configured to have a normalized drain-to-gate capacitance at the direct current drain-to-source bias voltage, and to have a second normalized drain-to-gate capacitance at two-thirds the direct current drain-to-source bias voltage, where the second normalized drain-to-gate capacitance is less than twice the first normalized drain-to-gate capacitance.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: May 16, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Qianli Mu, Zulhazmi Mokhti, Jia Guo, Scott Sheppard
  • Patent number: 11652461
    Abstract: A transistor device includes a transistor cell comprising a channel region, a gate runner that is electrically connected to a gate electrode on the channel region and physically separated from the gate electrode, and a harmonic termination circuit electrically connected to the gate runner between the gate electrode and an input terminal of the transistor device, the harmonic termination circuit configured to terminate signals at a harmonic frequency of a fundamental operating frequency of the transistor device.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: May 16, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Frank Trang, Zulhazmi Mokhti, Guillaume Bigny
  • Patent number: 11621672
    Abstract: A circuit includes a field effect transistor (FET), a reference transistor having an output coupled to an output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal for the reference transistor in response to a change in drain current of the reference transistor due to carrier trapping and to apply the input signal to an input of the reference transistor, and a summing node coupled to an input of the FET and to the input of the reference transistor. The summing node adds the input signal to an input signal of the FET to compensate the carrier trapping effect.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: April 4, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Young-Youl Song, Zulhazmi A. Mokhti, John Wood, Qianli Mu, Jeremy Fisher
  • Publication number: 20230040260
    Abstract: A circuit includes a field effect transistor (FET), a reference transistor having an output coupled to an output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal for the reference transistor in response to a change in drain current of the reference transistor due to carrier trapping and to apply the input signal to an input of the reference transistor, and a summing node coupled to an input of the FET and to the input of the reference transistor. The summing node adds the input signal to an input signal of the FET to compensate the carrier trapping effect.
    Type: Application
    Filed: August 5, 2021
    Publication date: February 9, 2023
    Inventors: Young-Youl Song, Zulhazmi A. Mokhti, John Wood, Qianli Mu, Jeremy Fisher
  • Publication number: 20220302271
    Abstract: A transistor device includes a gate finger and a drain finger extending on a semiconductor structure, a gate bond pad coupled to the gate finger, and a drain bond pad coupled to the drain finger. The gate bond pad extends on the gate finger and the drain finger.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Inventors: Frank Trang, Zulhazmi Mokhti, Haedong Jang
  • Publication number: 20220302272
    Abstract: Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a drain finger extending on the semiconductor structure in a first direction, and a drain interconnect extending in the first direction and configured to be coupled to a drain signal at an interior position of the drain interconnect, where the drain interconnect is connected to the drain finger at a position offset from the interior position of the drain interconnect.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Inventors: Frank Trang, Zulhazmi Mokhti, Haedong Jang
  • Patent number: 11424333
    Abstract: Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a gate finger extending on the semiconductor structure in a first direction, and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an interior position of the gate interconnect, where the gate interconnect is connected to the gate finger at a position offset from the interior position of the gate interconnect.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: August 23, 2022
    Assignee: WolfSpeed, Inc.
    Inventors: Frank Trang, Zulhazmi Mokhti, Haedong Jang
  • Patent number: 11417617
    Abstract: Packaged transistor devices are provided that include a transistor on a base of the packaged transistor device, the transistor comprising a control terminal and an output terminal, a first bond wire electrically coupled between an input lead and the control terminal of the transistor, a second bond wire electrically coupled between an output lead and the output terminal of the transistor, and an isolation material that is and physically between the first bond wire and the second bond wire, wherein the isolation material is configured to reduce a coupling between the first bond wire and the second bond wire.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: August 16, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Frank Trang, Haedong Jang, Zulhazmi Mokhti
  • Patent number: 11417746
    Abstract: A transistor device includes a gate finger and a drain finger extending on a semiconductor structure, a gate bond pad coupled to the gate finger, and a drain bond pad coupled to the drain finger. The gate bond pad extends on the gate finger and/or the drain bond pad extends on the drain finger.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: August 16, 2022
    Assignee: WolfSpeed, Inc.
    Inventors: Frank Trang, Zulhazmi Mokhti, Haedong Jang
  • Patent number: 11387340
    Abstract: A transistor device includes a gate finger and a drain finger extending on a semiconductor structure, a gate bond pad coupled to the gate finger, and a drain bond pad coupled to the drain finger. The gate bond pad extends on the gate finger and/or the drain bond pad extends on the drain finger.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: July 12, 2022
    Assignee: WolfSpeed, Inc.
    Inventors: Frank Trang, Zulhazmi Mokhti, Haedong Jang
  • Patent number: 11387336
    Abstract: Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a gate finger extending on the semiconductor structure in a first direction, and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an interior position of the gate interconnect, where the gate interconnect is connected to the gate finger at a position offset from the interior position of the gate interconnect.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: July 12, 2022
    Assignee: WolfSpeed, Inc.
    Inventors: Frank Trang, Zulhazmi Mokhti, Haedong Jang
  • Publication number: 20220103130
    Abstract: Gallium nitride based RF transistor amplifiers include a semiconductor structure having a gallium nitride based channel layer and a gallium nitride based barrier layer thereon, and are configured to operate at a specific direct current drain-to-source bias voltage. These amplifiers are configured to have a normalized drain-to-gate capacitance at the direct current drain-to-source bias voltage, and to have a second normalized drain-to-gate capacitance at two-thirds the direct current drain-to-source bias voltage, where the second normalized drain-to-gate capacitance is less than twice the first normalized drain-to-gate capacitance.
    Type: Application
    Filed: December 9, 2021
    Publication date: March 31, 2022
    Inventors: Qianli Mu, Zulhazmi Mokhti, Jia Guo, Scott Sheppard
  • Patent number: 11239802
    Abstract: Gallium nitride based RF transistor amplifiers include a semiconductor structure having a gallium nitride based channel layer and a gallium nitride based barrier layer thereon, and are configured to operate at a specific direct current drain-to-source bias voltage. These amplifiers are configured to have a normalized drain-to-gate capacitance at the direct current drain-to-source bias voltage, and to have a second normalized drain-to-gate capacitance at two-thirds the direct current drain-to-source bias voltage, where the second normalized drain-to-gate capacitance is less than twice the first normalized drain-to-gate capacitance.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: February 1, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Qianli Mu, Zulhazmi Mokhti, Jia Guo, Scott Sheppard
  • Publication number: 20210351141
    Abstract: A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 11, 2021
    Inventors: Frank Trang, Qianli Mu, Haedong Jang, Zulhazmi Mokhti
  • Patent number: 11069635
    Abstract: A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: July 20, 2021
    Assignee: Cree, Inc.
    Inventors: Frank Trang, Qianli Mu, Haedong Jang, Zulhazmi Mokhti
  • Publication number: 20210104978
    Abstract: Gallium nitride based RF transistor amplifiers include a semiconductor structure having a gallium nitride based channel layer and a gallium nitride based barrier layer thereon, and are configured to operate at a specific direct current drain-to-source bias voltage. These amplifiers are configured to have a normalized drain-to-gate capacitance at the direct current drain-to-source bias voltage, and to have a second normalized drain-to-gate capacitance at two-thirds the direct current drain-to-source bias voltage, where the second normalized drain-to-gate capacitance is less than twice the first normalized drain-to-gate capacitance.
    Type: Application
    Filed: October 2, 2019
    Publication date: April 8, 2021
    Inventors: QIANLI MU, Zulhazmi Mokhti, Jia Guo, Scott Sheppard
  • Publication number: 20210083641
    Abstract: A transistor device includes a transistor cell comprising a channel region, a gate runner that is electrically connected to a gate electrode on the channel region and physically separated from the gate electrode, and a harmonic termination circuit electrically connected to the gate runner between the gate electrode and an input terminal of the transistor device, the harmonic termination circuit configured to terminate signals at a harmonic frequency of a fundamental operating frequency of the transistor device.
    Type: Application
    Filed: November 25, 2020
    Publication date: March 18, 2021
    Inventors: Frank Trang, Zulhazmi Mokhti, Guillaume Bigny
  • Publication number: 20200402933
    Abstract: Packaged transistor devices are provided that include a transistor on a base of the packaged transistor device, the transistor comprising a control terminal and an output terminal, a first bond wire electrically coupled between an input lead and the control terminal of the transistor, a second bond wire electrically coupled between an output lead and the output terminal of the transistor, and an isolation material that is and physically between the first bond wire and the second bond wire, wherein the isolation material is configured to reduce a coupling between the first bond wire and the second bond wire.
    Type: Application
    Filed: September 2, 2020
    Publication date: December 24, 2020
    Inventors: Frank Trang, Haedong Jang, Zulhazmi Mokhti