Low-frequency, high-gain amplifier with high DC-offset voltage tolerance

Abstract

The instrumentation amplifier circuit of the present invention is particularly suited for amplifying ECG signals, rejecting common mode signals and removing a DC offset. The preferred embodiment of the present invention basically comprises a front-stage differential amplifier, and a common-mode rejection circuit. By employing a twin-T network, the front stage differential amplifier is able to simultaneously remove the DC offset and achieve high gain using standard off-the-shelf components. The common mode differential gain, however, is zero, which is the desired result. The common-mode rejection circuit removes the common-mode signal to yield only the amplified ECG signal. The present amplifier circuit has a much greater DC offset tolerance than the prior art amplifier while the Common Mode Rejection Ratio (CMRR), residual noise at the output, and the input dynamic range is comparable to that of the prior art amplifier. Moreover, it requires fewer operational amplifiers.

Description

FIELD OF THE INVENTION

[0001] The present invention relates generally to the field of amplifier circuits, and in particular to low-frequency amplifier circuits.

BACKGROUND OF THE INVENTION

[0002] Amplifier circuits utilizing operational amplifiers are well known in the art. For such circuits, it is well understood that only the values of the surrounding impedances need to be properly selected to control the gain of the circuits. If a DC offset voltage needs to be removed from the input signal, a DC-blocking capacitor is added to the circuit. For most applications where the frequency of the input signal is not extremely low and the gain requirement is not very high, standard off-the-shelf components can be used for the amplifier.

[0003] In some instances, however, the input signal has extremely low frequency while the gain requirement is very high. An example of such a situation can be found in the instrumentation amplifier (IA) to be used for amplifying the electrical signals of the heart. The graphical recording to these heart signals is known as electrocardiograms (ECG). The instrumentation amplifier to be used for amplifying ECG signals must have the ability to reject DC offset voltages generated between a pair of ECG electrodes. The offset voltage results from unequal contact potentials at the electrode-skin interface caused by electrochemical half-cells which form when ions between the electrode and the skin interchange. The offset voltage, which is typically around 100 mV, is very large compared to the electrocardiogram signals which are around 1 mV.

[0004] Most IAs used for ECG provide the DC offset rejection capability by dividing the IA circuit into two stages—a low-gain DC differential amplifier at the front stage followed by a high gain AC amplifier. A typical IA circuitry is shown in FIG. 1 with a gain in the front stage, 5, being 20 and the gain in the back stage, 10, being 50, resulting in an overall gain of 1000 (or 1 V/mV amplification). The AC amplifier cut-off frequency is 0.05 Hz. Gains of 20 and 50 are typical for IAs. As can be seen from FIG. 1, the first stage also includes the circuitry, 15, for rejecting the common mode signal.

[0005] Analytically, it can be shown that the differential gain of the 1st stage of the amplifier in FIG. 1 is: 1 A DS = 1 + R 1 + R 2 R C

[0006] Since this gain has no frequency discrimination, both the ECG and the DC offset signals will be equally amplified. Because the DC offset voltage is much higher than the signal being amplified, it can be seen that the circuitry of FIG. 1 would certainly saturate the output, if the circuit is not divided into two stages. Although by adding a capacitor XC in series with RC frequency discrimination can be obtained, simultaneously achieving 0.05 Hz cut-off frequency and a high gain is currently impractical with standard off-the-shelf components.

[0007] The inclusion of the additional stage increases the number of operational amplifiers needed in the overall amplifier circuit. Moreover, it can shown that this prior art amplifier circuit has a low DC offset tolerance, and hence, any aberrant peak in the ECG signal may cause at least a portion of the output to saturate. Such a result is highly undesirable as the ECG reading may falsely indicate a condition in the heart which is, in fact, non-existent.

OBJECT OF THE INVENTION

[0008] It is an object of the present invention to overcome the shortcomings of the prior art amplifier.

[0009] Particularly, it is an object of the present invention to provide an amplifier circuit which can remove the DC offset while achieving high gain.

[0010] It is another object of the present invention to provide an amplifier circuit which minimizes the number of operation amplifiers used.

[0011] It is yet another object of the present invention to provide an amplifier circuit which can be made using all off-the-shelf components.

SUMMARY OF THE INVENTION

[0012] The instrumentation amplifier circuit of the present invention is particularly suited for amplifying ECG signals, rejecting common mode signals and removing a DC offset. The preferred embodiment of the present invention basically comprises a front-stage differential amplifier, and a common-mode rejection circuit. By employing a twin-T network, the front stage differential amplifier is able to simultaneously remove the DC offset and achieve high gain using standard off-the-shelf components. The common mode differential gain, however, is zero, which is the desired result. The common-mode rejection circuit removes the common-mode signal to yield only the amplified ECG signal. The present amplifier circuit has a much greater DC offset tolerance than the prior art amplifier while the Common Mode Rejection Ratio (CMRR), residual noise at the output, and the input dynamic range is comparable to that of the prior art amplifier. Moreover, it requires fewer operational amplifiers.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 is a schematic diagram of the prior art instrumentation amplifier circuitry using two stages for the amplification.

[0014] FIG. 2 is a schematic diagram of the present instrumentation amplifier circuitry using only a single stage for the amplification.

DETAILED DESCRIPTION OF THE INVENTION

[0015] Electrocardiogram (ECG) signals have a unique set of characteristics. Mainly the characteristics are low frequency and low amplitude with a relatively high DC offset in relation to the main signal, usually embedded in very strong common interference signal picked up from the mains power line. The instrumentation amplifier circuit of the present invention is particularly suited for amplifying ECG signals, rejecting common mode signals and removing the DC offset, and hence, the present invention shall be described in the context of ECG application as way of illustrating the preferred embodiment of the present invention. However, it should be understood that the present invention may be employed in other applications where the signal to be amplified displays a set of characteristics similar to those mentioned herein.

[0016] An ECG signal generally carries a voltage level around 1 mV and frequency bandwidth of 0.05 Hz to 100 Hz. The common mode interference signal may vary in amplitude up to 600 to 1000 mV operating at around power line frequencies (50 Hz or 60 Hz depending on the mains frequency used by the country). The DC offset may vary up to around 100 mV. It is generally required that the ECG signal be amplified about 1000 times. Hence the instrumentation amplifier needs to have the following characteristics: high gain; ability to remove the DC offset; reject the common mode signal.

[0017] The preferred embodiment of the present invention is shown in FIG. 2. The present instrumentation amplifier circuit 20 basically comprises a front-stage differential amplifier 21 using a twin T-feedback network, and a common-mode rejection circuit 22. Referring to FIG. 2, the differential amplifier 21 includes a first operating amplifier 24 and a second operating amplifier 32. The first operating amplifier has a non-inverting input 26, an inverting input 28, and an output 30. The second operating amplifier 32 has a non-inverting input 34, an inverting input 36, and an output 38. The non-inverting input 26 of the first operating amplifier 24 receives the differential input signal e2. The non-inverting input 34 of the second operating amplifier 32 receives the differential input signal el. The output 30 of the operating amplifier 24 outputs the differential output signal e4. The output 38 of the operating amplifier 32 outputs the differential output signal e3.

[0018] Connected in between the first operating amplifier 24 and the second operating amplifier 32 is the twin T-feedback network where the resistors R2 and R4 form the first “T” with the capacitor Cp and the resistor Rp, and where the resistors R1 and R3 form the second “T” with the resistor Rp and the capacitor Cp. Bridging the twin T-network is the resistor RC and the capacitor Cc. The resistor R4 is connected to the output 30 of the first operating amplifier 24, and the resistor R3 is connected to the output 38 of the second operating amplifier 32. The resistors R2 and Rc are connected to the inverting input 28 of the first operating amplifier 24, and the resistor R1 and the capacitor Cc are connected to the inverting input 36 of the second operating amplifier 32.

[0019] At the outputs 30 and 38, the common mode differential gain Ac is zero which is a desired characteristic of the ECG instrumentation amplifier. The differential gain of the amplifier at the outputs 30 and 38, however, is the following: 2 A DN = 1 + 2 ⁢ ( R 1 + R 3 ) ( R C - jX C ) + ( 2 ⁢ R 3 R p - jX p ) ⁢   ⁢ ( 1 + 2 ⁢ R 1 R C - jX C )

[0020] where XC and XP are the reactances of the capacitors CC and CP.

[0021] The equation reveals that the frequency discrimination exists, is of second order, and that it is practical to obtain high gain and low cut-off frequency. For instance, a gain of about 1000 and a cut-off frequency of 0.05 Hz was achieved using the following off-the-shelf components:

[0022] R1=4.7 M&OHgr;

[0023] R2=4.7 M&OHgr;

[0024] R3=4.7 M&OHgr;

[0025] R4=4.7 M&OHgr;

[0026] Rc=300 K&OHgr;

[0027] Rp=300 K&OHgr;

[0028] Xc=10 &mgr;F

[0029] Xp=10 &mgr;F

[0030] All operational amplifiers used were LF355.

[0031] To remove the common mode signal, a common mode rejection circuitry 22 is added to the front-stage amplifier circuitry 21. Referring to FIG. 2, the common mode rejection circuitry 22 is of a standard design which includes an operating amplifier 40 having a inverting input 42, non-inverting input 44, and an output Vout 46. Connecting the output 46 and the inverting input 42 is the resistor R8. Connecting the non-inverting input 44 and the ground 52 are the resistor R10 and the variable resistor VR1. The common mode rejection circuitry 22 is connected to the front-stage amplifier circuitry via the resistors R7 and R9. Together, the configuration of the resistors R7, R8, R9, R10, VR1 form a standard subtraction circuit with the operating amplifier 40. Its output 46 is thus the result of subtracting the signal at its negative input (i.e. output 30) from the signal at its positive input (i.e. output 38). VR1 is generally included to add to the value of R10 so as to compensate for the tolerance in standard component values. However, it is possible that VR1 may be omitted in certain circumstances. Although various off-the-shelf components are possible, the following components and values were used with good results:

[0032] R7=91 K&OHgr;

[0033] R8=91 K&OHgr;

[0034] R9=91 K&OHgr;

[0035] R10=81 K&OHgr;

[0036] VR1=25 K&OHgr;

[0037] In general, high performance subtraction is achieved whenever the values are closely matched as follows:

R7=R8=R9=R10+VR1

[0038] The experimental results showed that the present circuitry 20 performs at least equivalent to the prior art two-stage amplifier circuitry shown in FIG. 1 in many respects, and superiorly outperformed the prior art circuitry in its ability to tolerate DC offset. Some of the performance measurement comparisons are shown below: 1 Comparison Chart Measurements Prior Art Amplifier Present Amplifier CMRR (at 50 Hz) 100 dB 99 dB Residual Noise (at o/p) 40 mV pp 70 mV pp Input dynamic range −1.7 to +3.5 V −2.2 to +3.7 V DC Offset tolerance −0.17 to +0.21 V −3.2 to +3.18 V

[0039] As can be seen from the chart above, the present amplifier circuit has a much greater DC offset tolerance than the prior art amplifier while the Common Mode Rejection Ratio (CMRR), residual noise at the output, and the input dynamic range is comparable to that of the prior art amplifier.

[0040] The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. For instance, the subtractor circuit may be omitted in applications where the differential outputs are sufficient. For example, the differential outputs 30, 38 may be connected to the inputs of a differential input analogue-to-digital converter (ADC). The presently disclosed embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are, therefore, to be embraced therein.

Claims

1. An amplifier circuit comprising:

a first operational amplifier having a non-inverting input, an inverting input, and a differential output e4, said non-inverting input receiving a differential input signal e2;

a second operational amplifier having a non-inverting input, an inverting input, and a differential output e3, said non-inverting input receiving a differential input signal e1;

a twin T-feedback network including R1, R2, R3, R4, Rp, Cp, where the resistors R2 and R4 form the first “T” with the capacitor Cp and the resistor Rp, and where the resistors R1 and R3 form the second “T” with the resistor Rp and the capacitor Cp; and

a resistor RC and a capacitor Cc connected in series,

wherein the resistor R4 is connected to the output e4 of the first operating amplifier, the resistor R3 is connected to the output e3 of the second operating amplifier, the resistors R2 and Rc are connected to the inverting input of the first operating amplifier, and the resistor R1 and the capacitor Cc are connected to the inverting input of the second operating amplifier, and

wherein said e2 and e1 is a low frequency, low amplitude differential signal having a relatively high DC offset, and

wherein values for R1, R2, R3, R4, Rp, RC, Cc, and Cp are chosen to give said circuit a high gain at the differential outputs e3 and e4 and a cut-off frequency sufficient to remove said DC offset.

2. The amplifier circuit as recited in

claim 1 wherein said e1 and e2 are ECG signals.

3. The amplifier circuit as recited in

claim 1 wherein said values for R1, R2, R3, R4, Rp, RC, Cc, and Cp are approximately the following:

R1=4.7 M&OHgr;

R2=4.7 M&OHgr;

R3=4.7 M&OHgr;

R4=4.7 M&OHgr;

Rc=300 K&OHgr;

Rp=300 K&OHgr;

Xc=10 &mgr;F

Xp=10 &mgr;F

where XC and XP are the reactances of the capacitors CC and CP.

4. The amplifier circuit as recited in

claim 1 wherein said values for R1, R2, R3, R4, Rp, RC, Cc, and Cp are approximately the following:

R1=4.7 M&OHgr;

R2=4.7 M&OHgr;

R3=4.7M&OHgr;

R4=4.7 M&OHgr;

Rc=300 K&OHgr;

Rp=300 K&OHgr;

Xc=10 &mgr;F

Xp=10 &mgr;F

where XC and XP are the reactances of the capacitors CC and CP.

5. The amplifier circuit as recited in

claim 1 further comprising a common-mode rejection circuit connected to said differential outputs e3 and e4.

6. The amplifier circuit as recited in

claim 3 further comprising a common-mode rejection circuit connected to said differential outputs e3 and e4.

7. The amplifier circuit as recited in

claim 2 further comprising a common-mode rejection circuit connected to said differential outputs e3 and e4.

8. The amplifier circuit as recited in

claim 4 further comprising a common-mode rejection circuit connected to said differential outputs e3 and e4.

9. The amplifier circuit as recited in

claim 5 wherein said common-mode rejection circuit comprises a third operational amplifier having a inverting input, non-inverting input, and an output Vout.

a resistor R8, said resistor R8 connecting the output Vout and the inverting input,

a resistor R10 and a variable resistor VR1, said resistor R10 and said variable resistor VR1 connecting the non-inverting input and a ground;

a resistor R7 connecting said inverting input of said third operational amplifier with said output e4; and

a resistor R9 connecting said non-inverting input of said third operational amplifier with said output e3.

10. The amplifier circuit as recited in

claim 7 wherein said common-mode rejection circuit comprises a third operational amplifier having a inverting input, non-inverting input, and an output Vout.

a resistor R8, said resistor R8 connecting the output Vout and the inverting input,

a resistor R10 and a variable resistor VR1, said resistor R10 and said variable resistor VR1 connecting the non-inverting input and a ground;

a resistor R7 connecting said inverting input of said third operational amplifier with said output e4; and

a resistor R9 connecting said non-inverting input of said third operational amplifier with said output e3.

11. The amplifier circuit as recited in

claim 9 wherein following condition is substantially met: R7=R8=R9=R10+VR1.

12. The amplifier circuit as recited in

claim 10 wherein following condition is substantially met: R7=R8=R9=R10+VR1.

13. The amplifier circuit as recited in

claim 11 wherein values for said resistors and variable resistor are substantially as follows:

R7=91 K&OHgr;

R8=91 K&OHgr;

R9=91 K&OHgr;

R10=81 K&OHgr;

VR1=25 K&OHgr;.

14. The amplifier circuit as recited in

claim 12 wherein values for said resistors and variable resistor are substantially as follows:

R7=91 K&OHgr;

R8=91 K&OHgr;

R9=91 K&OHgr;

R10=81 K&OHgr;

VR1=25 K&OHgr;.