Sum And Difference Amplifiers Patents (Class 330/69)
  • Patent number: 11171620
    Abstract: A high-to-low voltage interface circuit includes a differential circuit stage with a differential amplifier circuit having inverting and non-inverting inputs coupled to first and second input pads as well as a differential output having first and second output nodes. A pair of bias amplifier stages sensitive to the common mode voltage of the differential amplifier circuit are arranged in first and second current mirror paths from the first and second input pads to the inverting/non-inverting inputs of the differential amplifier circuit, respectively. The bias amplifier stages are configured to maintain the first input pad and the second input pad of the differential circuit stage at the common mode voltage.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: November 9, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventor: Germano Nicollini
  • Patent number: 11004595
    Abstract: A coil component includes a body having one surface and the other surface opposing each other in one direction and a plurality of wall surfaces connecting the one surface and the other surface to each other, a coil part including a coil pattern embedded in the body and forming at least one turn about one direction, first and second external electrodes connected to the coil part, formed, respectively, on both end surfaces opposing each other among the plurality of wall surfaces of the body and extending to one surface of the body, a shielding layer including a cap part disposed on the other surface of the body and a side wall part disposed on each of the plurality of wall surfaces of the body except both the end surfaces of the body, an insulating layer formed between the body and the shielding layer, and a seed layer formed between the insulating layer and the shielding layer.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ju Hwan Yang, Byeong Cheol Moon, Byung Soo Kang
  • Patent number: 10979009
    Abstract: An embodiment of an amplifier circuit includes first, second, and third amplifiers. The first and second amplifiers, each of which can be a respective operational amplifier or a respective transconductance amplifier, are configured to amplify a differential input signal with a non-inverting gain. And the third amplifier, which can be an operational amplifier or a transconductance amplifier, is configured to cause the first and second amplifiers to amplify a common-mode input signal with a gain that is less than unity. The third amplifier can also be configured to cause the first and second amplifiers to generate a common-mode output voltage that is substantially independent of the common-mode input voltage. Consequently, in addition to presenting a high input impedance and a low noise factor, such an amplifier circuit has a configurable common-mode output voltage and has a lower common-mode gain (e.g., less than unity, approaching zero) than other non-inverting differential amplifiers.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: April 13, 2021
    Assignee: Honeywell International Inc.
    Inventor: Paul M Werking
  • Patent number: 10951186
    Abstract: Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes: a first channel configured to receive a first input signal and a second input signal and generate a first output signal and a second output signal based at least in part on the first input signal and the second input signal; and a second channel configured to receive a third input signal and a fourth input signal and generate a third output signal and a fourth output signal based at least in part on the third input signal and the fourth input signal. A first differential signal is equal to the first input signal minus the second input signal. A second differential signal is equal to the third input signal minus the fourth input signal. The first output signal corresponds to a first phase.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: March 16, 2021
    Assignee: On-Bright Electronics (Shanghai) Co., Ltd.
    Inventors: Tingzhi Yuan, Zibin Chen, Lieyi Fang
  • Patent number: 10931243
    Abstract: A signal coupling method and apparatus is disclosed. A coupling network is coupled to convey signals from first functional circuit block to a second functional circuit block. The coupling network includes a first signal path having a first capacitor for providing AC coupling between the first and second functional circuit blocks. The coupling network further includes a second signal path in parallel with the first signal path. The second signal path includes a switched capacitor circuit coupled to receive a first common mode voltage corresponding to the first functional circuit block and a second common mode voltage corresponding to the second functional circuit block.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: February 23, 2021
    Assignee: Apple Inc.
    Inventors: Vahid Majidzadeh Bafar, Mansour Keramat, Tao Wang
  • Patent number: 10911025
    Abstract: A second-order all-pass network has at least three Second Generation Current Conveyors (CCIIs). A network input is connected or connectable to a Y port of a first CCII, a Z port of the first CCII is connected to a Y port of a second CCII, an X port of the first CCII is connected to a Y port of a third CCII, and a network output is connected or connectable, directly or indirectly, to a Z port of the second CCII. The X port of the first CCII is connected via a first network element to ground, the Z port of the first CCII is connected via a second network element to ground, an X port of the third CCII is connected via a third network element to ground, and an X port of the second CCII is connected via a fourth network element to ground.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: February 2, 2021
    Assignee: University of Pretoria
    Inventors: Piotr Jan Osuch, Tinus Stander
  • Patent number: 10903808
    Abstract: Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes: a first channel configured to receive a first input signal and a second input signal and generate a first output signal and a second output signal based at least in part on the first input signal and the second input signal; and a second channel configured to receive a third input signal and a fourth input signal and generate a third output signal and a fourth output signal based at least in part on the third input signal and the fourth input signal. A first differential signal is equal to the first input signal minus the second input signal. A second differential signal is equal to the third input signal minus the fourth input signal. The first output signal corresponds to a first phase.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: January 26, 2021
    Assignee: On-Bright Electronics (Shanghai) Co., Ltd.
    Inventors: Tingzhi Yuan, Zibin Chen, Lieyi Fang
  • Patent number: 10797704
    Abstract: A differential signal transfer system includes a dynamic level-shifter and a common-mode rejection device. The dynamic level-shifter is configured to (a) receive an input signal including a differential-mode component and a first common-mode component and (b) generate a level-shifted signal from the input signal, the level-shifted signal including the differential-mode component and a second common-mode component that is different from the first common-mode component. The common-mode rejection device is configured to receive the level-shifted signal and generate an output signal therefrom, where the output signal includes the differential-mode component.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: October 6, 2020
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Pietro Filoramo, Angelo Genova
  • Patent number: 10749468
    Abstract: Certain aspects relate to a semiconductor die. The semiconductor die includes a voltage-controlled oscillator (VCO), wherein the VCO includes a resonant capacitor, and a resonant inductor coupled in parallel with the resonant capacitor. The resonant inductor includes a first elongated portion and a second elongated portion that are parallel with each other. The semiconductor die also includes a voltage supply line configured to route a supply voltage to the VCO, wherein the voltage supply line includes a first portion that runs parallel with the first and second elongated portions of the resonant inductor and is located between the first and second elongated portions of the resonant inductor.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: August 18, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Ji-Hoon Park, Yido Koo, Jeongsik Yang, Wei-Han Cho, Xiaoyu Wang
  • Patent number: 10698550
    Abstract: The present disclosure provides a capacitance detection circuit, which includes a front end circuit and a processing circuit; where the front end circuit comprises a first driving circuit, a first cancel circuit and a PGA circuit, the first driving circuit, the first cancel circuit and the PGA circuit are connected to a first end of a detection capacitor, a second end of the detection capacitor is grounded, and the processing circuit is connected to an output end of the front end circuit, and configured to determine a capacitance variation of a capacitance of the detection capacitor with respect to the base capacitance according to a voltage signal output by the front end circuit.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: June 30, 2020
    Assignee: SHENZHEN WEITONGBO TECHNOLOGY CO., LTD.
    Inventors: Guangkai Yuan, Hong Jiang, Guopao Li
  • Patent number: 10693306
    Abstract: A circuit includes a signal processor configured to perform a signal processing, an amplifier configured to amplify a signal output from the signal processor, a first power supply path connected from a battery to the signal processor, a second power supply path connected from the battery to the amplifier, a capacitor connected to the second power supply path and that assists power supplied to the amplifier, and a power limiter connected to the second power supply path and that limits input power supplied from the battery.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: June 23, 2020
    Assignee: YAMAHA CORPORATION
    Inventor: Jun Ishii
  • Patent number: 10660575
    Abstract: A sensor circuit usable with capacitive sensors in an electrical potential sensing network is provided. The sensor circuit provides bias current while maintaining a high input impedance for signals in a frequency band of interest by positive feedback of a filtered measurement through a finite impedance. The sensor circuits are suited for technologies such as, but not limited to electroencephalography (EEG), electromyography (EMG) and electrocardiograms (ECG). A neurofeedback system utilizing the capacitive conduction sensor is also described.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: May 26, 2020
    Assignee: Zengar Institute Inc.
    Inventor: Kenneth MacCallum
  • Patent number: 10341038
    Abstract: A passive optical network system having a node that is optically coupled to optical line terminals (OLTs), and that is optically coupled to optical network units (ONUs). The node includes at least one fiber link module (FLM), each FLM including an upstream multiplex conversion device (MCD), and a downstream MCD. The upstream MCD receives an upstream optical signal from the ONUs, converts the upstream optical signal to an upstream electrical signal, and transmits a regenerated upstream optical signal to the OLTs. The downstream MCD receives a downstream optical signal from the OLTs, converts the downstream optical signal to a downstream electrical signal, and transmits a regenerated downstream optical signal to the ONUs.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: July 2, 2019
    Assignee: ARRIS Enterprises LLC
    Inventors: David B. Bowler, Xinfa Ma
  • Patent number: 10320346
    Abstract: In a general aspect, a current sense amplifier circuit (CSA) can include a null amplifier path and a main amplifier path that are both configured to receive a differential input voltage. The null amplifier path can output a first differential output voltage based on the differential input voltage. The main amplifier path can also be configured to receive the first differential output voltage and output a second differential output voltage based on the differential input voltage and the first differential output voltage. The null and main amplifier paths can each include a differential amplifier having first and second input stages that are each configured to receive the differential input voltage. The first input stage and the second input stage of the main amplifier path can and be powered by a respective (first and second) floating voltage supply rails that are referenced to a floating ground rail.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: June 11, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Razvan Puscasu
  • Patent number: 10135406
    Abstract: A new compensation system for an audio input reduces noise by matching feedback ratios in the positive and negative paths. A variable resistance network allows for fine control of resistance trimming in one of the signal paths, which allows for compensation between tolerance of resistors that are external to an integrated circuit and those that are internal to the integrated circuit.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: November 20, 2018
    Assignee: Avnera Corporation
    Inventors: Ali Hadiashar, Wai Laing Lee
  • Patent number: 10044328
    Abstract: A transimpedance amplifier that includes an input configured to receive a current input from an upstream device and output configured to present an output voltage. The current input may be from a photodetector or any other device that is part of an optical signal receiving unit front end. In one configuration, there are three amplifier stages in the transimpedance amplifier connected in series. A feedback path with feedback resistor connects between the input and output of the transimpedance amplifier. A bandwidth extender circuit connects between a stage output and a stage input of the transimpedance amplifier. In a three stage embodiment, the bandwidth extender circuit extends between an input of the second stage and the output of the second stage. The bandwidth extender includes at least one active device configured to provide positive feedback to increase gain. The bandwidth extender circuit is able to be automatically or selectively deactivated to filter unwanted frequency components.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: August 7, 2018
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventor: Michael P. Khaw
  • Patent number: 10043454
    Abstract: A source driver circuit is provided that supplies, to each of pixels arranged in a matrix, an electrical signal corresponding to a pixel signal. The source driver circuit includes a reference voltage generating unit, which includes a plurality of resistors connected in series, and a resistor, for gradation voltage generation that divides an input voltage into voltages of magnitudes. The source driver circuit also includes a gradation voltage generating circuit, which is connected between the plurality of resistors and is also connected between the plurality of resistors and the resistor for gradation voltage generation, that includes an offset-canceling amplifier. The offset-canceling amplifier alternates between an offset extraction state, in which an offset voltage of the offset-canceling amplifier is extracted, and a buffer output state, in which the offset voltage is added to the pixel signal and outputted.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: August 7, 2018
    Assignee: JOLED INC.
    Inventor: Hirofumi Nakagawa
  • Patent number: 10038412
    Abstract: The application relates to the field of communications technologies, and disclose a signal amplification processing method and apparatus. The method includes setting multiple groups of parameter values for a signal decomposition parameter group, separately performing signal amplification processing based on each group of parameter values, obtaining a power amplification efficiency corresponding to each group of parameter values, obtaining a group of parameter values corresponding to a maximum power amplification efficiency in the power amplification efficiency corresponding to each group of parameter values, and setting the group of parameter values corresponding to the maximum power amplification efficiency as parameter values of the signal decomposition parameter group. Thus, the power amplification efficiency may be improved.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: July 31, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Wei Huang, Xiang Feng
  • Patent number: 10027514
    Abstract: A system comprises a first module and a second module, connected by a transmission line comprising first and second wires. The first module includes common mode voltage circuitry, for imposing a common mode voltage onto the first and second wires. The first module includes signal generation circuitry, for generating a signal voltage in response to first data, and for imposing the signal voltage as a differential signal onto the first and second wires during periods when the first module has first data to transmit. The second module includes current generation circuitry, for generating a signal current in response to second data, and for injecting the signal current as a differential current onto the first and second wires during periods when the second module has second data to transmit. The first module includes respective resistances connected to the first and second wires.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 17, 2018
    Assignee: Cirrus Logic, Inc.
    Inventors: Willem Zwart, Bhupendra Singh Manola
  • Patent number: 10020784
    Abstract: A TIA includes first and second input terminals for differentially receiving an input current signal, and first and second amplification circuits. The first amplification circuit includes a first Alternating-Current (AC) path and a first Direct-Current (DC) path that are configured to amplify in parallel respective first AC and DC components of the input current signal flowing via the first input terminal, and a first combiner configured to sum the amplified first AC and DC components. The second amplification circuit includes a second AC path and a second DC path that are configured to amplify in parallel respective second AC and DC components of the input current signal flowing via the second input terminal, and a second combiner configured to sum the amplified second AC and DC components. First and second output terminals are configured for outputting an output voltage signal formed between outputs of the first and second combiners.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: July 10, 2018
    Assignee: MELLANOX TECHNOLOGIES DENMARK APS
    Inventors: Kenn Christensen, Steen Bak Christensen
  • Patent number: 9949028
    Abstract: The present invention relates to a device for measuring an electric current generated by an acoustic amplifier in order to actuate an acoustic speaker comprising: a resistor (1) positioned in series between the amplifier and the speaker; a voltage-to-current converter (3), the inputs of which are connected to the terminals of the resistor (1), and which proportionally converts the difference in voltage across the terminals of the shunt to a signal current; a first current mirror (7), the input of which is connected to the output of the voltage-to-current converter (3) and the output of which is connected to a current-to-voltage converter (5); a constant bias current generator (9) connected to an input of the voltage-to-current converter (3) and the output of which is connected to the current-to-voltage converter (5) via a second current mirror (11), and capable of generating a bias current such that the device operates in linear mode and without saturation regardless of the electric current generated by th
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: April 17, 2018
    Assignee: L-ACOUSTICS
    Inventors: M. Christian Heil, Pierre Vaysse
  • Patent number: 9941848
    Abstract: In accordance with embodiments of the present disclosure, a transconductance with capacitances feedback compensation amplifier may include a capacitor in parallel with an inner feedback loop of the amplifier for providing cascade compensation to the amplifier.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: April 10, 2018
    Assignee: Cirrus Logic, Inc.
    Inventors: Ramin Zanbaghi, Aaron Brennan, Johann Gaboriau, Prashanth Drakshapalli, Vamsikrishna Parupalli
  • Patent number: 9917558
    Abstract: Apparatus and methods for a difference amplifier are provided. In certain examples, the difference amplifier can provide high common mode rejection without differential signal attenuation. In an example, a difference amplifier circuit can include first and second amplifiers, first and second buffer amplifiers, a first feedback voltage divider coupled between an output of the first buffer amplifier and an output of the second amplifier, and a second feedback voltage divider coupled between an output of the second buffer amplifier and an output of the first amplifier.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: March 13, 2018
    Assignee: Analog Devices Global
    Inventor: Andreas Koch
  • Patent number: 9778124
    Abstract: Certain implementations of the disclosed technology may include systems, methods, and apparatus for a sealed transducer with an adjustment port. The sealed transducer may include one or more terminals. A first terminal may include electrical connections for connecting to an input voltage source, a ground, and for providing a transducer output signal. A second terminal, for example, may include an electrical port for connecting to an external and separately sealed adjustment network. In one example implementation, the adjustment network can include one or more components configured to couple with internal circuitry of the transducer to alter a response of the transducer.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: October 3, 2017
    Assignee: Kulite Semiconductor Products, Inc.
    Inventor: Wolf Landmann
  • Patent number: 9710411
    Abstract: A signal conditioner can include a state machine configured to detect a predetermined protocol level mode of a data signal on a bi-directional serial bus. The signal conditioner can also include a re-driver configured to inject current into at least one of a rising edge and a falling edge of the data signal on the bi-directional serial bus in response to the detection of the predetermined protocol level mode.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: July 18, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Win Naing Maung, Yonghui Tang, Suzanne Mary Vining, Hao Liu
  • Patent number: 9698741
    Abstract: A chopper stabilzed amplifier with synchronous switched capacitor noise filtering is disclosed. In an exemplary embodiment, an apparatus includes a chopper amplifier having an input that receives an input signal and an output that outputs an amplified signal. The chopper amplifier includes an input chopping circuit and an output chopping circuit, where the input and output chopping circuits operate in response to a chop clock. The apparatus also includes a switched capacitor filter having an input that receives the amplified signal and an output that outputs a filtered signal. The switched capacitor filter operates in response to a filter clock. The apparatus also includes a filter timing adjuster that receives a reference voltage and adjusts a phase of the filter clock with respect to the chop clock to reduce chopper noise on that reference voltage.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: July 4, 2017
    Assignee: IXYS Corporation
    Inventor: Eric Blom
  • Patent number: 9650670
    Abstract: A polynucleotide sequencer comprising an integrated and multiplexed network of patch clamp capacitive integrator-differentiator amplifiers with small feedback capacitors using pseudo-resistors.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: May 16, 2017
    Assignee: The Regents of the University of California
    Inventors: Jungsuk Kim, William Dunbar
  • Patent number: 9608580
    Abstract: A biosignal apparatus is described including an amplifier and a sampler. The amplifier is configured to alternate between an operating state and a low power state based on a periodically changing control signal. The sampler is configured to sample a signal output from the amplifier in response to the amplifier being in the operating state and maintain the sampled signal in response to the amplifier being in the low power state.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: March 28, 2017
    Assignees: Samsung Electronics Co., Ltd., The Industry & Academic Cooperation in Chungnam National University (IAC)
    Inventors: Hyoung Ho Ko, Jong Pal Kim, Tak Hyung Lee
  • Patent number: 9608691
    Abstract: Methods and systems for modulating an amplifier power supply to efficiently attain amplified RF output power with much lower power dissipation than existing amplifiers. In a cable television (CATV) network, a processor receives a signal to be amplified by an amplifier at a location remote from the processor. A bias point of the amplifier may be variably modulated based on peaks of an input signal to reduce amplifier dissipation.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: March 28, 2017
    Assignee: ARRIS Enterprises, Inc.
    Inventors: Marcel F. Schemmann, Zoran Maricevic
  • Patent number: 9473074
    Abstract: A chopper stabilized amplifier with synchronous switched capacitor noise filtering is disclosed. In an exemplary embodiment, an apparatus includes a chopper amplifier having an input that receives an input signal and an output that outputs an amplified signal. The chopper amplifier includes an input chopping circuit and an output chopping circuit, where the input and output chopping circuits operate in response to a chop clock. The apparatus also includes a switched capacitor filter having an input that receives the amplified signal and an output that outputs a filtered signal. The switched capacitor filter operates in response to a filter clock. The apparatus also includes a filter timing adjuster that receives a reference voltage and adjusts a phase of the filter clock with respect to the chop clock to reduce chopper noise on that reference voltage.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: October 18, 2016
    Assignee: IXYS Corporation
    Inventor: Eric Blom
  • Patent number: 9391571
    Abstract: In one embodiment a chopper-stabilized amplifier may be formed to include a symmetrical passive RC notch filter having two cut-off frequencies. In an embodiment, the chopper stabilized amplifier may use only two clock signals to control the chopping operations.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: July 12, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Cornel D. Stanescu
  • Patent number: 9362874
    Abstract: An apparatus comprises a differential amplifier circuit and a current source. The differential amplifier circuit is configured to receive a voltage at an input, wherein the differential amplifier circuit generates an output voltage having a magnitude proportional to the received voltage over a voltage range to be measured at a specified output common mode voltage. The current source is electrically connected to an input of the differential amplifier circuit and is configured to subtract a midpoint of a voltage range of the battery voltage to be measured at the input of the differential amplifier, wherein a circuit supply voltage provided to the differential amplifier circuit and the current source is less than the voltage at the input.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: June 7, 2016
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Hrvoje Jasa, Andrew M. Jordan
  • Patent number: 9321454
    Abstract: A method for operating a vehicle includes: specifying a time-related target power demand for the vehicle to an internal combustion engine; and switching in an additional powering device in addition to the internal combustion engine when a time-related actual power demand of the vehicle on the internal combustion engine deviates from the time-related target power demand. The present invention makes it possible to operate the internal combustion engine in a diagnosis mode largely independently of the specific driving situation.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: April 26, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventors: Uta Fischer, Udo Schulz, Rainer Schnurr
  • Patent number: 9319004
    Abstract: Apparatus and methods for equalization are provided. In certain implementations, an equalizer includes first and second feedback resistors, first and second equalization resistors, an equalization capacitor, and an amplification circuit that includes first to fourth input terminals and first and second output terminals. The amplification circuit can receive a differential input voltage signal between the first and third input terminals, and the first and second equalization resistors and the equalization capacitor are electrically connected in series between the second and fourth input terminals with the equalization capacitor between the first and second equalization resistors. Additionally, the first feedback resistor is electrically connected between the first output terminal and the second input terminal, and the second feedback resistor is electrically connected between the second output terminal and the fourth input terminal.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: April 19, 2016
    Assignee: Analog Devices, Inc.
    Inventors: Abhishek Bandyopadhyay, David Paul Foley
  • Patent number: 9300253
    Abstract: An amplifier includes a first transformer configured to output first differential signals, a first differential amplifier coupled to the first transformer, a second transformer coupled to the first differential amplifier, a second differential amplifier coupled to the second transformer, a third transformer configured to transform second differential signals output from the second differential amplifier to a single-ended output signal, and a first bias circuit configured to supply a first bias voltage to a first secondary coil of the first transformer, wherein the first bias circuit sets the first bias voltage to a voltage greater than or equal to a first voltage based on the input signal in a first operating area where power of the output signal is greater than or equal to a first power so that power-gain characteristics of the output signal become closer to characteristics where gain of the output signal becomes constant.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: March 29, 2016
    Assignee: Socionext Inc.
    Inventor: Nobumasa Hasegawa
  • Patent number: 9264002
    Abstract: In certain applications, differential amplifiers with infinite common mode rejection ratios are desirable. However, resistance mismatches due to imperfections in the manufacturing create finite common mode rejection ratio in differential amplifiers degrading their performance. Disclosed are apparatus and method for improving the common mode rejection ratio of practical differential amplifiers.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: February 16, 2016
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Jinhua Ni, Dan Li
  • Patent number: 9118286
    Abstract: A DC offset cancellation circuit is provided. The DC offset cancellation circuit includes a first operational amplifier and a feedback gain circuit. The first operational amplifier includes a first input transconductance stage, a second input transconductance stage and an output stage. An input terminal of the first input transconductance stage receives an input signal of the first operational amplifier through a first input terminal of the first operational amplifier. An output terminal of the output stage outputs an output signal of the first operational amplifier through an output terminal of the first operational amplifier. An input terminal of the feedback gain circuit is coupled to the output terminal of the first operational amplifier, and an output terminal of the feedback gain circuit is coupled to the input terminal of the second transconductance stage through a second input terminal of the first operational amplifier.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: August 25, 2015
    Assignee: Novatek Microelectronics Corp.
    Inventor: Shiau-Wen Kao
  • Patent number: 9100128
    Abstract: A method for enabling AC coupling or DC coupling when receiving burst data signals comprises generating a hold-over pattern, wherein the hold-over pattern is a AC balanced pattern when an AC coupling is required and a low-logic value signal when a DC coupling is required; inputting the generated hold-over pattern to an AC coupling circuit, when no burst data signal is received; inputting only a received burst data signal to the AC coupling circuit, during the reception of such signal; and upon receiving of the entire burst data signal, generating a reset signal causing to input the generated holdover pattern to an AC coupling circuit.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: August 4, 2015
    Assignee: Broadcom Corporation
    Inventor: Amiad Dvir
  • Patent number: 9093896
    Abstract: A multi-power domain operational amplifier includes an input stage circuit, a power domain transforming circuit and an active load. The input stage circuit is configured to transform a set of input voltages into a set of input currents in a first power domain. The power domain transforming circuit is configured to transform the set of input currents into a set of output currents in a second power domain. The active load is configured to generate an output voltage according to the set of output currents. A common mode range of the output voltage is shifted as compared with a common mode range of the set of input voltages.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: July 28, 2015
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Min-Hung Hu, Chiu-Huang Huang, Chen-Tsung Wu
  • Patent number: 9024685
    Abstract: In some embodiments, a pilot signal generation circuit is provided including a buffer and a differential amplifier responsive to an output of the buffer. A first transistor is connected to control a reference voltage at an input of the buffer in response to a pulse width modulated logic signal and a second transistor connected to control a reference voltage at an input of the differential amplifier based on the pulse width modulated logic signal such that the second transistor is connected so as to turn on when the first transistor is turned off and to turn off when the first transistor is turned on. The differential amplifier is configured to provide at an output a pilot signal proportional to a gain of the differential amplifier.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: May 5, 2015
    Assignee: AeroVironment, Inc.
    Inventor: Albert Flack
  • Patent number: 8988145
    Abstract: A high fidelity current dumping audio amplifier in which for achieving the best performance are combined the feedforward error correction and the negative feedback. The principle of feedforward error correction in a balanced bridge in A.C. is used, including the whole audio frequency amplifier, combined with a classical negative feedback that includes the items of the amplification chain likely to introduce distortions. The amplifier can be built in a current amplifier structure or in a voltage amplifier structure. The current amplifier structure contains an operational amplifier used as a voltage-current converter and signal de-phasing, two low power symmetrical current amplifiers operating in “A” class with a current mirror structure and a power stage in “B” class, with no quiescent current. The voltage structure of the amplifier contains an operational voltage amplifier, a low power amplifier operating in “A” class, and a power stage operating in “B” class.
    Type: Grant
    Filed: November 24, 2012
    Date of Patent: March 24, 2015
    Inventor: Barbu Popescu
  • Patent number: 8933751
    Abstract: A first trimming capacitor having a first terminal and a second terminal is coupled in parallel between a first terminal and a second terminal of a first capacitor. The first trimming capacitor comprises a first plurality of switched capacitors having different capacitances coupled in parallel. Each of the switched capacitors comprises a switch capacitor and a switch coupled in series. In an illustrative application the first capacitor and the first trimming capacitor are coupled between an output terminal of an operational amplifier (op-amp) and an inverting input terminal of the op-amp. A second capacitor and a second trimming capacitor similar to the first capacitor and the first trimming capacitor are coupled between an input and the inverting input terminal of the op-amp.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: January 13, 2015
    Assignee: Altera Corporation
    Inventors: Wilson Wong, Weiqi Ding, Shuxian Chen, Simardeep Maangat, Albert Ratnakumar
  • Patent number: 8928398
    Abstract: The even order harmonic distortion in a differential circuit is reduced or eliminated by treating the amplitude and phase mismatch sources that cause the distortion as impedance mismatches, and utilizing switched resistor circuitry that adjusts the load resistance to reduce the effects of the amplitude mismatch sources, and switched capacitor circuitry that adds shunt capacitance to reduce the effects of the phase mismatch sources.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: January 6, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Bumha Lee, Yongseon Koh
  • Publication number: 20150002221
    Abstract: An instrumentation amplifier includes a first amplifier having one input connected to a first input of the instrumentation amplifier, a second amplifier having one input connected to a second input of the instrumentation amplifier, and a feedback network. The feedback network including an active filter having a first low pass filter characteristic with a first cut-off frequency in respect of differential mode signals at the first and second inputs of the instrumentation amplifier, and a second low pass filter characteristic with a second cut-off frequency in respect of common mode signals at the first and second inputs of the instrumentation amplifier. The disclosure also relates to a device for acquiring biopotential signals and a signal amplification method.
    Type: Application
    Filed: June 26, 2014
    Publication date: January 1, 2015
    Applicant: IMEC VZW
    Inventors: Nick Van Helleputte, Refet Firat Yazicioglu
  • Patent number: 8922275
    Abstract: A common mode bias circuit may include a weak common mode bias generator and a common mode bias capacitance. During a first state of the common mode bias circuit, the weak common mode bias generator may be coupled to the common mode bias capacitance and may impart to them a predefined common mode signal level. During a second state of the common mode bias circuit, the common mode bias capacitance may be coupled to differential inputs of an amplifier in a manner that establishes an input common mode level for the amplifier.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: December 30, 2014
    Assignee: Linear Technology Corporation
    Inventor: Dave Thomas
  • Publication number: 20140354354
    Abstract: A circuit can include operational amplifier having a first input, a second input, and an output, first and second resistors in series between the output of the op-amp and a ground, and multiple switches configurable to toggle the circuit between a positive phase and a negative phase.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 4, 2014
    Applicant: Keithley Instruments, Inc.
    Inventor: Wayne C. Goeke
  • Patent number: 8854126
    Abstract: A semiconductor device includes: an amplifier circuit that has an inverting input terminal, a non-inverting input terminal, and an output terminal; a first variable voltage source that generates a first bias voltage having a voltage value corresponding to a first set value; a second variable voltage source that generates a second bias voltage having a voltage value corresponding to a second set value; a first resistor whose one end is connected to the inverting input terminal; a second resistor that is connected between the output terminal and the inverting input terminal; a third resistor whose one end is connected to the non-inverting input terminal; and a fourth resistor that is connected between the second variable voltage source and the non-inverting input terminal. The first bias voltage is provided to the other end of the first resistor. An input signal is provided to the other end of the third resistor.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: October 7, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Junichi Ishigami, Yasuhiro Koga
  • Patent number: 8854125
    Abstract: A linear amplifier that comprises a signal input terminal that receives an input signal having a first common mode voltage, a voltage amplifier having a non-inverting input terminal that receives a second common mode voltage, a first and a second input resistance connected in series from the signal input terminal to the inverting input terminal of the voltage amplifier, a feedback resistance connected between the inverting input terminal and the output terminal of the voltage amplifier, and a constant current source. The constant current source supplies a constant current to a middle node between the first and the second input resistances. The constant current generates a voltage drop, which is equal to a difference between the first and the second common mode voltages, across the first input resistance. Accordingly, the common mode voltage of the output signal is directly determined by the second common mode voltage.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: October 7, 2014
    Assignee: MegaChips Corporation
    Inventor: Takashi Ikeda
  • Patent number: 8847812
    Abstract: In a time-to-digital conversion stage, a time-to-digital conversion circuit outputs an n-bit digital signal, which represents an integer value ranging from ?(2n-1?1) to +(2n-1?1), based on a phase difference between a first and a second signals input thereto; a time difference amplifier circuit amplifies the phase difference between the first and the second signals 2n-1 times, and outputs two signals having an amplified phase difference therebetween; a delay adjustment circuit adds a phase difference dependent on the digital signal to the two signals output from the time difference amplifier circuit, and outputs another two signals; an output detection circuit detects that the delay adjustment circuit has output the another two signals, and outputs a detection signal; and a storage circuit latches the digital signal in synchronism with the detection signal. Multi-stage coupling of the time-to-digital conversion stages forms a pipeline time-to-digital converter.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: September 30, 2014
    Assignee: Panasonic Corporation
    Inventors: Shiro Dosho, Takuji Miki
  • Publication number: 20140269834
    Abstract: A circuit arrangement may include: a first bipolar transistor; a second bipolar transistor; wherein the circuit arrangement is configured to provide a first current flowing through the first bipolar transistor and a second current flowing through the second bipolar transistor; a resistor connected between a first input of the first bipolar transistor and a first input of the second bipolar transistor; a first circuit configured to provide a first current flowing through the resistor to a first input node of the first bipolar transistor, and a second circuit configured to provide a reference current to the first input node of the first bipolar transistor, wherein the first current and the reference current have different temperature dependencies.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Inventor: Matthias Eberlein