Abstract: Described are an amplifier circuits, systems, and methods for amplifying a plurality of sinusoid signals having a relative phase difference to each other. The amplifier circuit comprises a first sequence of at least three transistor amplifiers, wherein a first terminal of each transistor amplifier of the first sequence is configured to receive one respective signal of the plurality sinusoid signals. The amplifier further comprises a second sequence of at least three transistor amplifiers. A second terminal of each transistor amplifier of the second sequence is connected to a third terminal of one respective transistor amplifier of the first sequence. A first terminal of each transistor amplifier of the second sequence is connected to the third terminal of a next transistor amplifier of the second sequence. The first terminal of a last transistor amplifier is connected to the third terminal of a first transistor amplifier.

Abstract: An apparatus is comprised of a processor, a fast-locking Phase-Locked Loop Waveform Generator (PLLWG), an amplifier circuit, and a voltage controlled oscillator (VCO). The processor generates data program signals to program the PLLWG and generates a trigger command signal instructing the PLLWG to generate an analog tuning signal. The PLLWG, coupled to the processor, generates the analog tuning signal based on the trigger command signal. The amplifier circuit, coupled to the PLLWG, receives the analog tuning signal, amplify the analog tuning signal, and generates a control voltage. The VCO, coupled to the amplifier circuit, receives the control voltage and amplifies the control voltage to generate an amplified Radio Frequency (RF) channel frequency signal.

Abstract: Aspects of the present disclosure relate to apparatus and methods for dynamically adjusting the common-mode input signal of a power amplifier, such as a class-D power amplifier. One example power amplifier circuit generally includes a first amplifier having a signal input and a power input; and a common-mode adjustment circuit having a first input coupled to the power input of the first amplifier, having an output coupled to the signal input of the first amplifier, and being configured to generate a common-mode signal to apply to the signal input of the first amplifier, based on a power supply voltage on the power input of the first amplifier.

Abstract: In an embodiment, a current source is coupled to a first current terminal of a switch, the second current terminal of which is coupled to a first data line in a communication system. An edge detector has a first input, a second input, and an output, in which the first input is coupled to a second data line in the communication system, the second input is coupled to the first data line, and the output is coupled to a control terminal of the switch. The first and second data lines may be positive and negative data lines, respectively, of the communication system.

Abstract: A fully-differential amplifier (FDA) includes a core differential amplifier and a common-mode input voltage control circuit. The core differential amplifier includes differential inputs. The common-mode input voltage control circuit is coupled to the differential inputs. The common-mode input voltage control circuit is configured to generate an error signal as a difference of an input common mode voltage at the differential inputs and a target common mode input voltage (VICM); and to adjust the input common mode voltage to the VICM based on the error signal.

Abstract: A current-mode transmitter amplifies a differential input signal to a differential, current-mode output signal. A split-input, current-mode-logic stage produces small, analog signals to limit switching currents and thus power consumption and power-supply noise. These small, analog signals are driven through a source-follower stage to reduce loading and shift the common-mode voltage to a desired level. A switched-current-source H-bridge driver combines differential outputs from the source-follower stage to provide an amplified differential output current. The output swing from the H-bridge driver is controlled by the voltage level from the source follower and derived from a replica-bias structure.

Abstract: A delay-compensating power management circuit is provided. The power management circuit includes a power management integrated circuit (PMIC) configured to generate a time-variant voltage(s) based on a time-variant target voltage(s) for amplifying an analog signal(s) associated with a time-variant power envelope(s). A voltage processing circuit is provided in the power management circuit to determine a temporal offset, which can be positive or negative, between the time-variant power envelope(s) and the time-variant target voltage(s). Accordingly, the voltage processing circuit modifies the time-variant target voltage(s) to substantially reduce the determined temporal offset and thereby realign the time-variant target voltage(s) with the time-variant power envelope(s). By realigning the time variant target voltage(s) with the time-variant power envelope(s), it is possible to align the time-variant voltage(s) with the time-variant power envelope(s) to reduce distortions (e.g.

Abstract: Embodiments of the present disclosure provide a chopper amplifier circuit that includes an operational amplifier, and a notch filter to be operated by a chopping pulse. The notch filter has a first branch that has a first capacitor, and a second branch that has a second capacitor. A chopping delay switch is connected to the first branch and the second branch of the notch filter. A control circuit is to close the chopping delay switch to short-circuit the first branch and the second branch of the notch filter to each other. The control circuit is to detect establishment of feedback signal at the chopper amplifier. The control circuit is to open the chopping delay switch, responsive to detecting establishment of the feedback signal at the chopper amplifier.

Abstract: The present disclosure relates to a device comprising two error amplifier stages having their first inputs interconnected, their second inputs interconnected and their outputs coupled to an output of the device, each stage comprising an operational amplifier; a circuit for calibrating the amplifier; a switch coupling an input of the amplifier to the first input; a switch coupling another input of the amplifier to the second input; a switch coupling an output of the amplifier to the stage output; a switch having on state which short-circuits the inputs of the amplifier; and a switch coupling the output of the amplifier to the calibration circuit.

Abstract: A universal serial bus (USB) signal transmission device, an operation method thereof, and a USB cable are provided. The USB signal transmission device includes a signal processing circuit, a switch circuit, and a control circuit. A first terminal of the switch circuit is coupled to a first USB circuit. A second terminal of the switch circuit is coupled to a second USB circuit. The control circuit turns off the switch circuit during a detection period to detect both terminals of the switch circuit to obtain a detection result. The control circuit turns on the switch circuit during a transmission period, and controls a transmission direction of the signal processing circuit according to the detection result.

Abstract: Devices, systems, and methods for multi-channel common-mode coupled alternating current (AC) gain amplifiers (MC-CM-AC Amp) are disclosed. The MC-CM-AC Amp can comprise a first operational amplifier including: a first non-inverting input port configured to be coupled to a first input signal, and a first inverting input port configured to be coupled to a first capacitor. The MC-CM-AC Amp can comprise a second operational amplifier including a second non-inverting input port configured to be coupled to a second input signal, and a second inverting input port configured to be coupled to a second capacitor. The MC-CM-AC Amp can comprise one or more gain-setting resistors configured to be coupled between the first capacitor and the second capacitor.

Abstract: A music sync low frequency stimulator can includes a speaker for outputting a plurality of first sound source signals, a sound source signal separator for separating at least one of the plurality of first sound source signals, a low frequency signal generator for generating a low frequency signal, and a music sync unit for controlling the strength and frequency of a low frequency signal according to at least one of second sound source signals separated by the sound source signal separator.

Abstract: Systems and methods are provided for detecting and analyzing changes in a body. A system includes an electric field generator, an external sensor device, a quadrature demodulator, and a controller. The electric field generator is configured to generate an electric field that associates with a body. The external sensor device sends information to the electric field generator and is configured to detect a physical change in the body in the electric field, where the physical change causes a frequency change of the electric field. The quadrature demodulator receives the electric field from the electric field generator and is configured to detect the frequency change of the electric field and to produce a detected response. The controller, coupled to the electric field generator, is configured to output a frequency control signal to the electric field generator and to modify the frequency of the electric field by adjusting the frequency control signal.

Abstract: A method operates a hearing device which performs active noise suppression for suppressing noise signals having one or more frequency components. An audiogram is provided which specifies a hearing threshold of a user of the hearing device as a function of frequency, wherein by using the audiogram it is determined which frequency components of the noise are audible to the user and which are not audible. The noise suppression is operated selectively by suppressing audible frequency components of the noise and by not suppressing inaudible frequency components of the noise. A corresponding hearing device is operated according to the method.

Abstract: The present teachings relate to an electronic device comprising: a first module for generating an audio signal; a second module for generating an ultrasonic signal; a mixer for generating a combined signal; a transmitter for outputting an acoustic signal dependent upon the combined signal; and, a processing means for controlling the ultrasonic signal; wherein, in response to receiving a first instruction signal for initiating the ultrasonic signal, the processing means is configured to increase the amount of the ultrasonic signal in the combined signal from an essentially zero value to a predetermined value over a predetermined enable time-period.

Abstract: Techniques, systems, architectures, and methods for amplifying the time difference between events detected on a focal plane array, allowing greater resolution than that afforded by a reference clock are herein disclosed.

Abstract: An apparatus is comprised of a processor, a fast-locking Phase-Locked Loop Waveform Generator (PLLWG), an amplifier circuit, and a voltage controlled oscillator (VCO). The processor generates data program signals to program the PLLWG and generates a trigger command signal instructing the PLLWG to generate an analog tuning signal. The PLLWG, coupled to the processor, generates the analog tuning signal based on the trigger command signal. The amplifier circuit, coupled to the PLLWG, receives the analog tuning signal, amplify the analog tuning signal, and generates a control voltage. The VCO, coupled to the amplifier circuit, receives the control voltage and amplifies the control voltage to generate an amplified Radio Frequency (RF) channel frequency signal.

Abstract: A voltage detection circuit includes a differential amplification circuit and a microcontroller unit (MCU). The MCU detects a differential voltage output from operational amplifiers of the differential amplification circuit, and calculates an internal resistance value of a battery cell based on the detected differential voltage. At this time, the MCU controls an amplification factor adjustment circuit of the differential amplification circuit based on a maximum voltage representing the highest voltage detectable by the MCU and the differential voltage output from the differential amplification circuit so as to set the amplification factor of the operational amplifiers.

Abstract: The present teachings relate to an electronic device comprising: a first module for generating an audio signal; a second module for generating an ultrasonic signal; a mixer for generating a combined signal; a transmitter for outputting an acoustic signal dependent upon the combined signal; and, a processing means for controlling the ultrasonic signal; wherein, in response to receiving a first instruction signal for initiating the ultrasonic signal, the processing means is configured to increase the amount of the ultrasonic signal in the combined signal from an essentially zero value to a predetermined value over a predetermined enable time-period.

Abstract: A receiver circuit includes an analog front end and a non-linear equalizer. The analog front end including a super source follower (SSF) amplifier having a first input terminal adapted to couple to a transmission line to receive an input signal referenced to a first voltage level, a second input adapted to receive a reference voltage, and first and second output terminals adapted to provide an amplified signal referenced to a second voltage level. The non-linear equalizer coupled to receive an output signal of the analog front end and compensate for inter-symbol interference at a data rate of at least 14 Gbps. The SSF amplifier includes transistors having relative sizes selected to provide a frequency response of the SSF amplifier with a peak at a frequency approximately ? of the data rate.

Abstract: A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.

Abstract: A differential to single-ended buffer amplifier with a swing suppression resistor in the differential amplification architecture is shown. The differential to single-ended buffer amplifier has a positive input terminal, a negative input terminal, a differential to single-ended operational amplifier (DISO op amp), and a swing suppression resistor. The DISO op amp has a non-inverting input terminal and an inverting input terminal respectively coupled to the positive input terminal and the negative input terminal, and it has a single-ended output terminal that outputs the output signal of the differential to single-ended buffer amplifier. The swing suppression resistor is connected between the negative input terminal of the differential to single-ended buffer amplifier and the non-inverting input terminal of the DISO op amp.

Abstract: This application relates to physiological monitoring typically for health and fitness purposes. Specifically, this application targets health and fitness monitors that require low noise acquisition of low amplitude biopotential signals. The method herein allows measurement and acquisition of biopotential signals that are normally too small to resolve due to the noise floor limitations of modern low noise amplifiers. Examples of applications that this method enables include monitoring devices located in far proximity from the location in which a biopotential signal originates, such as a wrist worn cardiac monitor, or a device that needs to sense low amplitude, fine muscle or nerve activity in a localized region.

Abstract: A receiver front-end circuit and an operating method thereof are disclosed. The receiver front-end circuit includes a common-mode suppression circuit and a rear-stage circuit. The common-mode suppression circuit is used to receive an external input common-mode voltage signal and perform common-mode noise suppression processing on the external input common-mode voltage signal, and then output an internal input common-mode voltage signal. The rear-stage circuit is coupled to the common-mode suppression circuit and used to receive the internal input common-mode voltage signal. The dynamic swing of the internal input common-mode voltage signal is smaller than the dynamic swing of the external input common-mode voltage signal.

Abstract: A high-to-low voltage interface circuit includes a differential circuit stage with a differential amplifier circuit having inverting and non-inverting inputs coupled to first and second input pads as well as a differential output having first and second output nodes. A pair of bias amplifier stages sensitive to the common mode voltage of the differential amplifier circuit are arranged in first and second current mirror paths from the first and second input pads to the inverting/non-inverting inputs of the differential amplifier circuit, respectively. The bias amplifier stages are configured to maintain the first input pad and the second input pad of the differential circuit stage at the common mode voltage.

Abstract: A coil component includes a body having one surface and the other surface opposing each other in one direction and a plurality of wall surfaces connecting the one surface and the other surface to each other, a coil part including a coil pattern embedded in the body and forming at least one turn about one direction, first and second external electrodes connected to the coil part, formed, respectively, on both end surfaces opposing each other among the plurality of wall surfaces of the body and extending to one surface of the body, a shielding layer including a cap part disposed on the other surface of the body and a side wall part disposed on each of the plurality of wall surfaces of the body except both the end surfaces of the body, an insulating layer formed between the body and the shielding layer, and a seed layer formed between the insulating layer and the shielding layer.

Abstract: An embodiment of an amplifier circuit includes first, second, and third amplifiers. The first and second amplifiers, each of which can be a respective operational amplifier or a respective transconductance amplifier, are configured to amplify a differential input signal with a non-inverting gain. And the third amplifier, which can be an operational amplifier or a transconductance amplifier, is configured to cause the first and second amplifiers to amplify a common-mode input signal with a gain that is less than unity. The third amplifier can also be configured to cause the first and second amplifiers to generate a common-mode output voltage that is substantially independent of the common-mode input voltage. Consequently, in addition to presenting a high input impedance and a low noise factor, such an amplifier circuit has a configurable common-mode output voltage and has a lower common-mode gain (e.g., less than unity, approaching zero) than other non-inverting differential amplifiers.

Abstract: Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes: a first channel configured to receive a first input signal and a second input signal and generate a first output signal and a second output signal based at least in part on the first input signal and the second input signal; and a second channel configured to receive a third input signal and a fourth input signal and generate a third output signal and a fourth output signal based at least in part on the third input signal and the fourth input signal. A first differential signal is equal to the first input signal minus the second input signal. A second differential signal is equal to the third input signal minus the fourth input signal. The first output signal corresponds to a first phase.

Abstract: A signal coupling method and apparatus is disclosed. A coupling network is coupled to convey signals from first functional circuit block to a second functional circuit block. The coupling network includes a first signal path having a first capacitor for providing AC coupling between the first and second functional circuit blocks. The coupling network further includes a second signal path in parallel with the first signal path. The second signal path includes a switched capacitor circuit coupled to receive a first common mode voltage corresponding to the first functional circuit block and a second common mode voltage corresponding to the second functional circuit block.

Abstract: A second-order all-pass network has at least three Second Generation Current Conveyors (CCIIs). A network input is connected or connectable to a Y port of a first CCII, a Z port of the first CCII is connected to a Y port of a second CCII, an X port of the first CCII is connected to a Y port of a third CCII, and a network output is connected or connectable, directly or indirectly, to a Z port of the second CCII. The X port of the first CCII is connected via a first network element to ground, the Z port of the first CCII is connected via a second network element to ground, an X port of the third CCII is connected via a third network element to ground, and an X port of the second CCII is connected via a fourth network element to ground.

Abstract: Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes: a first channel configured to receive a first input signal and a second input signal and generate a first output signal and a second output signal based at least in part on the first input signal and the second input signal; and a second channel configured to receive a third input signal and a fourth input signal and generate a third output signal and a fourth output signal based at least in part on the third input signal and the fourth input signal. A first differential signal is equal to the first input signal minus the second input signal. A second differential signal is equal to the third input signal minus the fourth input signal. The first output signal corresponds to a first phase.

Abstract: A differential signal transfer system includes a dynamic level-shifter and a common-mode rejection device. The dynamic level-shifter is configured to (a) receive an input signal including a differential-mode component and a first common-mode component and (b) generate a level-shifted signal from the input signal, the level-shifted signal including the differential-mode component and a second common-mode component that is different from the first common-mode component. The common-mode rejection device is configured to receive the level-shifted signal and generate an output signal therefrom, where the output signal includes the differential-mode component.

Abstract: Certain aspects relate to a semiconductor die. The semiconductor die includes a voltage-controlled oscillator (VCO), wherein the VCO includes a resonant capacitor, and a resonant inductor coupled in parallel with the resonant capacitor. The resonant inductor includes a first elongated portion and a second elongated portion that are parallel with each other. The semiconductor die also includes a voltage supply line configured to route a supply voltage to the VCO, wherein the voltage supply line includes a first portion that runs parallel with the first and second elongated portions of the resonant inductor and is located between the first and second elongated portions of the resonant inductor.

Abstract: The present disclosure provides a capacitance detection circuit, which includes a front end circuit and a processing circuit; where the front end circuit comprises a first driving circuit, a first cancel circuit and a PGA circuit, the first driving circuit, the first cancel circuit and the PGA circuit are connected to a first end of a detection capacitor, a second end of the detection capacitor is grounded, and the processing circuit is connected to an output end of the front end circuit, and configured to determine a capacitance variation of a capacitance of the detection capacitor with respect to the base capacitance according to a voltage signal output by the front end circuit.

Abstract: A circuit includes a signal processor configured to perform a signal processing, an amplifier configured to amplify a signal output from the signal processor, a first power supply path connected from a battery to the signal processor, a second power supply path connected from the battery to the amplifier, a capacitor connected to the second power supply path and that assists power supplied to the amplifier, and a power limiter connected to the second power supply path and that limits input power supplied from the battery.

Abstract: A sensor circuit usable with capacitive sensors in an electrical potential sensing network is provided. The sensor circuit provides bias current while maintaining a high input impedance for signals in a frequency band of interest by positive feedback of a filtered measurement through a finite impedance. The sensor circuits are suited for technologies such as, but not limited to electroencephalography (EEG), electromyography (EMG) and electrocardiograms (ECG). A neurofeedback system utilizing the capacitive conduction sensor is also described.

Abstract: A passive optical network system having a node that is optically coupled to optical line terminals (OLTs), and that is optically coupled to optical network units (ONUs). The node includes at least one fiber link module (FLM), each FLM including an upstream multiplex conversion device (MCD), and a downstream MCD. The upstream MCD receives an upstream optical signal from the ONUs, converts the upstream optical signal to an upstream electrical signal, and transmits a regenerated upstream optical signal to the OLTs. The downstream MCD receives a downstream optical signal from the OLTs, converts the downstream optical signal to a downstream electrical signal, and transmits a regenerated downstream optical signal to the ONUs.

Abstract: In a general aspect, a current sense amplifier circuit (CSA) can include a null amplifier path and a main amplifier path that are both configured to receive a differential input voltage. The null amplifier path can output a first differential output voltage based on the differential input voltage. The main amplifier path can also be configured to receive the first differential output voltage and output a second differential output voltage based on the differential input voltage and the first differential output voltage. The null and main amplifier paths can each include a differential amplifier having first and second input stages that are each configured to receive the differential input voltage. The first input stage and the second input stage of the main amplifier path can and be powered by a respective (first and second) floating voltage supply rails that are referenced to a floating ground rail.

Abstract: A new compensation system for an audio input reduces noise by matching feedback ratios in the positive and negative paths. A variable resistance network allows for fine control of resistance trimming in one of the signal paths, which allows for compensation between tolerance of resistors that are external to an integrated circuit and those that are internal to the integrated circuit.

Abstract: A transimpedance amplifier that includes an input configured to receive a current input from an upstream device and output configured to present an output voltage. The current input may be from a photodetector or any other device that is part of an optical signal receiving unit front end. In one configuration, there are three amplifier stages in the transimpedance amplifier connected in series. A feedback path with feedback resistor connects between the input and output of the transimpedance amplifier. A bandwidth extender circuit connects between a stage output and a stage input of the transimpedance amplifier. In a three stage embodiment, the bandwidth extender circuit extends between an input of the second stage and the output of the second stage. The bandwidth extender includes at least one active device configured to provide positive feedback to increase gain. The bandwidth extender circuit is able to be automatically or selectively deactivated to filter unwanted frequency components.

Abstract: A source driver circuit is provided that supplies, to each of pixels arranged in a matrix, an electrical signal corresponding to a pixel signal. The source driver circuit includes a reference voltage generating unit, which includes a plurality of resistors connected in series, and a resistor, for gradation voltage generation that divides an input voltage into voltages of magnitudes. The source driver circuit also includes a gradation voltage generating circuit, which is connected between the plurality of resistors and is also connected between the plurality of resistors and the resistor for gradation voltage generation, that includes an offset-canceling amplifier. The offset-canceling amplifier alternates between an offset extraction state, in which an offset voltage of the offset-canceling amplifier is extracted, and a buffer output state, in which the offset voltage is added to the pixel signal and outputted.

Abstract: The application relates to the field of communications technologies, and disclose a signal amplification processing method and apparatus. The method includes setting multiple groups of parameter values for a signal decomposition parameter group, separately performing signal amplification processing based on each group of parameter values, obtaining a power amplification efficiency corresponding to each group of parameter values, obtaining a group of parameter values corresponding to a maximum power amplification efficiency in the power amplification efficiency corresponding to each group of parameter values, and setting the group of parameter values corresponding to the maximum power amplification efficiency as parameter values of the signal decomposition parameter group. Thus, the power amplification efficiency may be improved.

Abstract: A system comprises a first module and a second module, connected by a transmission line comprising first and second wires. The first module includes common mode voltage circuitry, for imposing a common mode voltage onto the first and second wires. The first module includes signal generation circuitry, for generating a signal voltage in response to first data, and for imposing the signal voltage as a differential signal onto the first and second wires during periods when the first module has first data to transmit. The second module includes current generation circuitry, for generating a signal current in response to second data, and for injecting the signal current as a differential current onto the first and second wires during periods when the second module has second data to transmit. The first module includes respective resistances connected to the first and second wires.

Abstract: A TIA includes first and second input terminals for differentially receiving an input current signal, and first and second amplification circuits. The first amplification circuit includes a first Alternating-Current (AC) path and a first Direct-Current (DC) path that are configured to amplify in parallel respective first AC and DC components of the input current signal flowing via the first input terminal, and a first combiner configured to sum the amplified first AC and DC components. The second amplification circuit includes a second AC path and a second DC path that are configured to amplify in parallel respective second AC and DC components of the input current signal flowing via the second input terminal, and a second combiner configured to sum the amplified second AC and DC components. First and second output terminals are configured for outputting an output voltage signal formed between outputs of the first and second combiners.

Abstract: The present invention relates to a device for measuring an electric current generated by an acoustic amplifier in order to actuate an acoustic speaker comprising: a resistor (1) positioned in series between the amplifier and the speaker; a voltage-to-current converter (3), the inputs of which are connected to the terminals of the resistor (1), and which proportionally converts the difference in voltage across the terminals of the shunt to a signal current; a first current mirror (7), the input of which is connected to the output of the voltage-to-current converter (3) and the output of which is connected to a current-to-voltage converter (5); a constant bias current generator (9) connected to an input of the voltage-to-current converter (3) and the output of which is connected to the current-to-voltage converter (5) via a second current mirror (11), and capable of generating a bias current such that the device operates in linear mode and without saturation regardless of the electric current generated by th

Abstract: In accordance with embodiments of the present disclosure, a transconductance with capacitances feedback compensation amplifier may include a capacitor in parallel with an inner feedback loop of the amplifier for providing cascade compensation to the amplifier.

Abstract: Apparatus and methods for a difference amplifier are provided. In certain examples, the difference amplifier can provide high common mode rejection without differential signal attenuation. In an example, a difference amplifier circuit can include first and second amplifiers, first and second buffer amplifiers, a first feedback voltage divider coupled between an output of the first buffer amplifier and an output of the second amplifier, and a second feedback voltage divider coupled between an output of the second buffer amplifier and an output of the first amplifier.

Abstract: Certain implementations of the disclosed technology may include systems, methods, and apparatus for a sealed transducer with an adjustment port. The sealed transducer may include one or more terminals. A first terminal may include electrical connections for connecting to an input voltage source, a ground, and for providing a transducer output signal. A second terminal, for example, may include an electrical port for connecting to an external and separately sealed adjustment network. In one example implementation, the adjustment network can include one or more components configured to couple with internal circuitry of the transducer to alter a response of the transducer.

Abstract: A signal conditioner can include a state machine configured to detect a predetermined protocol level mode of a data signal on a bi-directional serial bus. The signal conditioner can also include a re-driver configured to inject current into at least one of a rising edge and a falling edge of the data signal on the bi-directional serial bus in response to the detection of the predetermined protocol level mode.

Abstract: A chopper stabilzed amplifier with synchronous switched capacitor noise filtering is disclosed. In an exemplary embodiment, an apparatus includes a chopper amplifier having an input that receives an input signal and an output that outputs an amplified signal. The chopper amplifier includes an input chopping circuit and an output chopping circuit, where the input and output chopping circuits operate in response to a chop clock. The apparatus also includes a switched capacitor filter having an input that receives the amplified signal and an output that outputs a filtered signal. The switched capacitor filter operates in response to a filter clock. The apparatus also includes a filter timing adjuster that receives a reference voltage and adjusts a phase of the filter clock with respect to the chop clock to reduce chopper noise on that reference voltage.