Addition circuits

Abstract

A method of designing an addition circuit, and an addition circuit designed according to the method are described. The design technique is optimised to facilitate design of an addition circuit of minimum depth. The design technique takes into account the number of logical stages of the addition circuit and the manner in which those stages are connected by spanning paths to create fan-out nodes. The number of fan-out nodes per level can be optimized. For bit lengths n, the number (m+2) of logical stages is n=2m+1 and for bit lengths n not of a binary order, the number (m+2) of logical stages is nbo=2m+1, where nbo is the next largest binary order after n.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to addition circuits for adding a binary number A to a binary number B, and more particularly but not exclusively to addition circuits designed to meet particular process or application criteria.

BACKGROUND OF THE INVENTION

[0002] A variety of different addition circuits are known. One basic example is illustrated in FIG. 1. The binary number A is represented as a series of bits ai where i is the binary weight of the bit ai and increases from the value zero for the least significant bit of A in steps of one to the value of the most significant bit of A. The binary number B is a series of bits bi where i is the binary weight of the bit. The summation of the numbers A and B is represented by the binary number S which is a series of bits si where i is the binary weight of the bit, and C8 which is the msb of the sum.

[0003] The bit a0 and the bit b0 are supplied as inputs to an AND gate 20 which produces the bit generate g0. The bit a0 and the bit b0 are also supplied as inputs to an XOR gate 40 which produces so as its output. The bit a1 and the bit b1 are supplied as inputs to an XOR gate 41 which produces the first bit propagate signal p1. The bit generate signal go and the first bit propagate signal p1 are supplied as inputs to an XOR gate 241 which produces the bit s1. The bit a1 and the bit b1 are also supplied as inputs to an OR gate 61 which supplies its output as a first input to an AND gate 81. The second input of the AND gate 81 is received from the output of the AND gate 20. The output of the AND gate 81 provides a first input to an OR gate 101. The second input to the OR gate 101 is received from an AND gate 21 which receives as inputs the bit a1 and the bit b1. The bit a2 and the bit b2 are supplied as inputs to an XOR gate 42 which provides its output as a first input to a XOR gate 242. The second input to the XOR gate 242 is provided by the output of the OR gate 101. The output of the XOR gate 242 provides the bit s2. The bit a2 and the bit b2 are also combined in an OR gate 62 to produce a first input to an AND gate 82 which receives as a second input the output from the OR gate 101.

[0004] The output from the AND gate 82 supplied as a first input to a OR gate 102. The second input to the OR gate 102 is supplied by a AND gate 22 which receives as an input the bits a2 and b2. The output of the OR gate 102 is supplied as a first input to a XOR gate 243. The second input to the XOR gate 243 is supplied by the output of an XOR gate 43 which receives as inputs the bit a3 and the bit b3. The output of the XOR gate 243 provides the bit s3. An AND gate 23 also receives the bits a3 and b3 and provides its output as a first input to a OR gate 163. The second input to the OR gate 163 is provided by an AND gate 143 which receives as a first input the output from the AND gate 22 and as a second input the output from an OR gate 63 which receives as inputs the bit a3 and bit b3. The output from the OR gate 63 is also provided as a first input to an AND gate 123 which receives as a second input the output from the OR gate 62.

[0005] The output from the AND gate 123 is supplied as a first input to an AND gate 83 which receives as a second input the output from the OR gate 101. The output from the AND gate 83 and the output from the OR gate 163 are combined in an OR gate 103. A XOR gate 244 receives as a first input the output from the OR gate 103 and as a second input the output from an XOR gate 44 which receives as inputs the bit a4 and the bit b4. The XOR gate 244 produces the bit s4.

[0006] An OR gate 64 receives an inputs the bit a4 and bit b4 and provides its output as a first input to an AND gate 84. The AND gate 84 receives as its second input the output from the OR gate 103 and provides its output to a OR gate 104. The other input to the OR gate 104 is provided by an AND gate 24 which receives as inputs the bit a4 and the bit b4. An XOR gate 245 produces the bit s5 and receives as a first input the output from the OR gate 104 and receives as a second input the output from an XOR gate 45 which receives as inputs the bit a5 and the bit b5. An AND gate 125 receives as a first input the output from the OR gate 64 and an output from an OR gate 65 which receives as inputs the bit a5 and the bit b5.

[0007] An OR gate 165 receives as a first input the output from an AND gate 25 which receives as inputs the bit a5 and the bit b5 and as a second input receives the output from an AND gate 145 which itself receives as inputs the output from the AND gate 24 and the output from the OR gate 65. The output from the AND gate 125 is combined with the output from the OR gate 103 in an AND gate 85 to produce a first input to a first OR gate 105. The second input to the OR gate 105 is provided by the output from the OR gate 165.

[0008] The output from the OR gate 105 is provided as a first input to the XOR gate 246. The XOR gate 246 receives as a second input the output from the XOR gate 46 which receives as inputs the bit a6 and the bit b6. The XOR gate 246 produces as an output the bit s6.

[0009] An OR gate 66 receives as its inputs the bit a6 and the bit b6 and supplies its output as a first input to an AND gate 126. The second input to the AND gate 126 is supplied by the output of the AND gate 125 and the output of the AND gate 126 is supplied as a first input to an AND gate 86.

[0010] The output from the OR gate 66 is supplied as a first input to an AND gate 146. The AND gate 146 receives as a second input the output from the OR gate 165 and provides an output signal to a first input of an OR gate 166. The second input to the OR gate 166 is supplied by an AND gate 26 which receives as inputs the bit a6 and the bit b6. The AND gate 86 which receives as a first input the output from the AND gate 126 receives as a second input the output from the OR gate 103 and provides its output as a first input to an OR gate 106. The second input to the OR gate 106 is provided by the output of the OR gate 166.

[0011] The output of the OR gate 106 is provided as a first input to an XOR gate 247. The XOR gate 247 receives as a second input the output from an XOR gate 47 which receives as inputs the bit a and the bit b7. The XOR gate 247 produces the bit s7.

[0012] The bit a7 and the bit b7 are combined in an OR gate 67 to produce a first input to an AND gate 187 which receives as a second input the output from the OR gate 66. The output from the OR gate 67 is supplied as a first input to an AND gate 207. The AND gate 207 receives as a second input the output from the AND gate 26. The output from the AND gate 207 is supplied as a first input to an OR gate 227. The second input to the OR gate 227 is provided by a AND gate 27 which receives as its inputs the bit signal a7 and the bit signal b7.

[0013] An AND gate 147 receives as its inputs the output from the AND gate 187 and the output from the OR gate 165 and provides its output as a first input to an OR gate 167. The second input to the OR gate 167 is supplied by the output of the OR gate 227. The output of the OR gate 167 is provided as a first input to an OR gate 107. An AND gate 127 receives as its inputs the output from the AND gate 125 and the output from the AND gate 187. The output from the AND gate 127 is supplied as a first input to the AND gate 87. The AND gate 87 receives as a second input the output from the OR gate 103. The output from the AND gate 87 is supplied as a second input to the OR gate 107. The output of the OR gate 107 produces the last carry value c8.

[0014] An addition circuit that can quickly change between producing an output value A+B and output value A+B+1 or that can simultaneously provide an output value A+B and an output value A+B+1 is described in an earlier GB Patent Application No. 9813328.3.

[0015] The addition circuitry described in that application has a plurality of addition paths, with each addition path having inputs for receiving respectively bits ai, bi of the first and second binary numbers and output means for producing respectively bits si, s′i of third (A+B) and fourth (A+B+1) binary numbers.

[0016] By modification to the output means, the circuit can be configured to provide a number of different useful outputs, such as A+B or A+B+1; A+B and A+B+1; A−B and B−A; A−B or B−A; and modulus A−B. Thus, the circuit has a number of different useful applications.

[0017] Each addition path has a number of logical nodes in the depth direction of the circuit (input to output). Each set of nodes arranged widthwise of the circuit (that is in the direction of bit significance) forms a logical stage. Each adjacent pair of addition paths defines a column. An addition circuit of so-called “minimum depth” has the minimum number of logical stages which are required to add together the binary numbers according to their length n. Clearly, the greater the length n of binary numbers to be added, the higher is the number of stages even in a “minimum depth” circuit.

[0018] In developing a minimum depth circuit, clearly constraints are imposed on how the logical nodes can be interconnected. In GB Application No. 9813328.3, the circuit is designed so that each logical node is connected to as many logical nodes in the subsequent logical stage as possible. This connection is made via the addition path for the node and by one or more spanning path which crosses at least one column. The number of nodes in a subsequent stage to which a node of the preceding logical stage is connected by spanning paths is termed herein “fan-out”.

[0019] Thus, the circuit of the earlier application is designed with so-called maximum fan-out. This has the advantage of minimising the number of wires that are required to make the circuit, but has the disadvantage that delays between logical states are incurred as a result of the capacitance introduced by the large number of gates connected to particular wires, particularly in the later logical stages.

[0020] Another possibility is to interconnect a node of a logical stage to a unique single node of a subsequent stage, which has the advantage of reducing fan-out (to a fan-out of 1), but the disadvantage of requiring a large number of wires which increases the space requirement for the circuit.

SUMMARY OF THE INVENTION

[0021] It is desirable to be able to design an addition circuit to accommodate a number of different process and application criteria. In particular, it is desirable to facilitate the process of designing an addition circuit of minimum depth.

[0022] According to the invention there is provided an addition circuit for adding together two operands, for example, two binary numbers (A,B), each having a length of n bits. The circuit includes an array of logical nodes that are arranged so that each set of logical nodes extending widthwise of the circuit form a logical stage and each set of nodes extending depthwise of the circuits form an addition path, with each pair of adjacent addition paths forming a column. Spanning paths are arranged to interconnect selected logical nodes so that adjacent logical stages are connected via an interconnection level, each spanning path extending from a node in one stage across at least one column and being connected to a number f of fan-out nodes in a subsequent stage.

[0023] The circuit has one or more of the following configuration parameters:

[0024] i) for each interconnection level the number f of fan-out nodes lies in the range 1 to 2j, where j is the interconnection level index lying between 0 and m, 2j is the maximum fan-out number for that level, and there are m+2 logical stages;

[0025] ii) the fan-out f of nodes at each level is always no greater than the number f of fan-out nodes at a subsequent level,

[0026] iii) the number of columns across which a spanning path extends within an interconnection level is 2j; and

[0027] at least one level has a fan-out number f<2j and at least one level has a fan-out number f>1.

[0028] By defining a number of criteria for the addition circuit in terms of the configuration parameters referred to above, it is possible to design the addition circuit to suit the particular requirements at hand. That is, it allows designs to be constructed with fewer spanning wires and/or lower fan-out without significantly compromising speed requirements for a given circuit depth. The configuration parameters allow a number of design trade-offs to be considered each time resulting in an optimized addition circuit for the particular instant application.

[0029] The invention is particularly useful in the context of minimum depth addition circuits. For an addition circuit of minimum depth, the number (m+2) of logical stages is derived from the following equations:

[0030] n=2m+1 (where n is a binary order), and

[0031] nb0=2m+1 (where n is not a binary order and where nb0 is the next largest binary order after n).

[0032] In the described embodiment, each logical node comprises at least one logic gate that receives at least two signals representing bits of the same significance i in the binary numbers a, b to be added.

[0033] Each spanning path can convey one or more signals from a node of one significance in one logical stage to a node of a different significance in a subsequent logical stage.

[0034] Another aspect of the invention provides a method of designing an addition circuit for adding together two binary numbers (A,B) each of bit length n. The method includes:

[0035] determining the number (m+2) of logical stages in the addition circuit according to the following:

[0036] for bit length n of a binary order, n=2m+1 and for bit lengths that are not binary orders nb0=2m+1 where nb0 is the next largest binary order after n;

[0037] for each of said logical stages allocating a set of virtual nodes, the virtual nodes forming potential addition paths depthwise of the circuit and adjacent addition paths forming a column;

[0038] determining for each logical stage its expected input capacitance; and

[0039] defining spanning paths wherein the spanning paths constitute an interconnection level between adjacent logical stages, wherein definition of the spanning paths is carried out in accordance with the following configuration parameters and depending on the expected input capacitance of each stage:

[0040] i) for each interconnection level the number f of fan-out nodes in a subsequent stage to which a node of a preceding stage is connected lies in the range 1 to 2j, where j is the interconnection level index lying between 0 and m and 2j is the maximum fan-out number for that level,

[0041] ii) the fan-out f of nodes at each level is always no greater than the fan-out f of nodes at a subsequent level,

[0042] iii) the number of columns across which a spanning path extends within an interconnection level is 2j, and

[0043] at least one level has a fan-out number f<2j and at least one level has a fan-out number f>1.

[0044] A number of different specific examples are possible. By way of illustration, the following particular examples are mentioned, but this is in no way a comprehensive list of all of the possible options.

[0045] An addition circuit wherein the fan-out f=1 for more than one level.

[0046] An addition circuit wherein f=1 for all levels except the mth level.

[0047] An addition circuit wherein at least one level has maximum fan-out f=2j where j is not equal to m.

[0048] An addition circuit where the fan-out f=2 for at least two levels.

[0049] For a better understanding of the present invention and to understand how the same may be brought into effect, reference will now be made by way of example only to the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG. 1 illustrates prior art circuitry for producing A+B in more detail;

[0051] FIG. 2 illustrates the circuit of FIG. 1 but labelled to clearly denote the layout of the logical nodes;

[0052] FIGS. 3a to 3e are node diagrams for addition circuits where n-8;

[0053] FIGS. 4a to 4e illustrates addition circuits implementing node diagrams of FIGS. 3a to 3d respectively; and

[0054] FIGS. 5a through 5n are node diagrams for addition circuits where n=16.

DETAILED DESCRIPTION OF THE INVENTION

[0055] Referring to FIG. 2, shown therein is the overall layout of the known addition circuit already illustrated in FIG. 1. The bit significance 0 . . . 7 is labelled for each addition path moving from the right hand side to the left hand side widthwise of the circuit of FIG. 2. The circuit has a plurality of logical nodes which are labelled according to the following notation:

[0056] Ni,k where i is the bit significance of the node and k is an index defining the depth of the node within the addition circuit in a manner, which will become clearer in the following.

[0057] The nodes N are arranged so that each set of logical nodes extending widthwise of the circuit forms a logical stage. That is, the nodes N0,0 . . . N7,0 form logical stage k=0, the nodes N1,1, N3,1, N5,1 and N7,1 form the logical stage k=1; the nodes N2,2, N3,2, N6,2, N7,2 form the logical stage k=2; and the nodes N4,3 . . . N7,3 form logical stage k=3.

[0058] Depthwise of the circuit, each set of nodes forms an addition path. Each pair of adjacent addition paths constitutes a column labelled C1 to C7 in FIG. 2. The logical stages are interconnected by interconnection levels which are marked L0 to L2 in FIG. 2. Each interconnection level L0 to L3 comprises a number of spanning paths that are wires connecting a node N in a preceding stage to one or more nodes in a subsequent stage. Each spanning path can extend across one or more columns and comprise one or more wires for transferring one or more signals. In FIG. 2, the interconnection level L0 has spanning paths P0,0, P2,0, P4,0 and P6,0. P0,0 conveys a single signal from bit significance 0 to bit significance 1 across column C1. P2,0 conveys two signals from bit significance 2 to bit significance 3 across column 3. Similarly P4,0 and P6,0 each convey two signals across a single column.

[0059] The spanning paths in level 1, P1,1 and P5,1 respectively cross two columns. Also, they connect the node of stage 1 to two nodes of stage 2. The number of nodes in a subsequent stage to which a node of a preceding stage is connected by spanning paths is termed herein “fan-out”. Of course, there are also a number of connections between nodes vertically along an addition path. Thus, the interconnection level L1 has a fan-out of 2. Applying the same principles, it can be seen that the interconnection level L2 has a fan-out of 4, connecting the node N3,2 in stage 2 to each of the four nodes N4,3 . . . N7,3 in stage 3.

[0060] The composition of each node in terms of its logical gates and the function of those logical gates can be seen by comparing FIG. 2 with FIG. 1. For example, the node N2,0 comprises the two logic gates 62 and 22. As another example, the node N5,1 comprises the three logic gates 125, 145 and 165. It will be appreciated that the nodes of the first stage each include an Exclusive OR gate 40 . . . 47, and that the nodes of the first stage each include an Exclusive OR gate 240 . . . 247.

[0061] FIG. 3e illustrates a node diagram for the circuit of FIG. 2. In FIG. 3e, a complete array of eight by four “virtual” nodes is illustrated, each node being represented by a black dot. The spanning paths P are denoted by black lines. In the diagram of 3e, it is easier to see that the fan-out for interconnection level L0 is 1, the fan-out for interconnection level L1 is 2 and the fan-out for interconnection level L2 is 4. The circuit is therefore defined by the notation [4,2,1], which is the fan-out for each interconnection level, taking the lattermost interconnection level first.

[0062] As already mentioned, a problem that exists with this circuit is the high fan-out for the last and the next-to-the last level, which imposes signal delays through the interconnection levels. One way of avoiding this would be to construct a circuit along the lines illustrates in the node diagram of FIG. 3a. In that diagram, it can be readily seen that each interconnection level L0, L1 and L2 has a fan-out of 1. However, what is also clearly evident is the number of wires that are required to implement the circuit. It will be appreciated that the number of wires is related to the number of spanning paths P.

[0063] The inventor has determined that there are a number of other design options for a bit length of n=8 and a minimum depth addition circuit, which are illustrated in FIGS. 3b, 3c and 3d. In each of those figures, a complete array of eight by four “virtual” nodes is illustrated, each node N being represented by a black dot. Scanning paths P are denoted by a black line. The addition circuits of FIGS. 3b, 3c and 3d share the following characteristics.

[0064] i) For each interconnection level Lj, the number f of fan-out nodes lies in the range 1 to 2j. j denotes the interconnection level index. In the addition circuits of FIGS. 3b, 3c and 3d, j is 0, 1 or 2. 2j is the maximum fan-out number for a particular level.

[0065] ii) The number f of fan-out nodes at each level is always no greater than the number f of fan-out nodes at a subsequent level.

[0066] Thus, in FIG. 3b the fan-out for levels L0 and L1 is 1, and the fan-out for level L2 is 2. In FIG. 3c the fan-out for level L0 is 1 and the fan out for levels L1 and L2 is 2. In FIG. 3d, the fan-out for levels L0 and L1 is 1, and the fan-out for level L2 is 4.

[0067] iii) The number of columns across which a spanning path extends within an interconnection level is 2j. Thus, for an eight bit adder as illustrated in FIGS. 3b, 3c and 3d the spanning paths P0 in level L0 cross one column, the spanning paths P1 in level L1 cross two columns, and the spanning paths P2 at level L2 cross four columns.

[0068] The addition circuits of FIGS. 3b, 3c and 3d also share the parameters that at least one level has a fan-out number less than its maximum, and at least one level has a fan-out number greater than one. By allowing these criteria to be varied, addition circuits can be designed in accordance with the required parameters of any particular application. Where space is an important consideration, the number of wires can be reduced by using increased fan-out at different levels. Where capacitive delays are a problem, these can be reduced by reducing fan-out where possible and increasing the number of levels where fan-out is less than its maximum.

[0069] FIGS. 4b, 4c and 4d represent the circuit implementations of the node diagrams of FIGS. 3b, 3c and 3d respectively. In each of these circuit diagrams, the nodes marked N correspond to the nodes N illustrated by black dots connected by black lines in FIGS. 3b, 3c and 3d. The black dots in the node array diagrams of FIGS. 3b, 3c and 3d which are not connected by black lines do not of course find an equivalent in the circuit diagrams of FIGS. 4b, 4c and 4d. The configuration of logic gates for each node can be selected from those illustrated in the circuit of FIG. 2, depending on the number of input signals required to be combined at the node and whether these have come from a spanning path or an addition path of the same bit significance.

[0070] The principles of the invention can be readily extended to addition circuits for adding binary numbers of different lengths. The invention also applies to so-called minimum-depth addition circuits, where the number of stages in the addition circuit is determined according to the following criteria:

[0071] for bit lengths n of a binary order, the number m+2 of logical stages is derived from the following equation:

n=2m+1, and

[0072] for bit lengths n which are not binary orders, the number m+2 of logical stages is derived from the following equation: nbo=2m+1 where nbo is the next largest binary order after n.

[0073] As will be apparent, in the preceding example m=2, the number of interconnection levels (index j) is m+1=3 and the number of logical stages (index k) is m+2=4. FIGS. 5a to 5n illustrate possible addition circuits where n=16 and m=3. FIGS. 5b to 5m represent circuits in accordance with embodiments of the invention, that is circuits which follow the configuration parameters discussed above.

[0074] In designing an addition circuit using the node array diagrams illustrated in FIGS. 3 and 5 and conforming to the above-mentioned criteria, it will be appreciated that those zones that are empty of spanning paths can be quickly identified. Of course, it is not necessary to implement a logical node with logic circuitry where it is not connected to any other node.

[0075] A method of designing an addition circuit will now be described. The binary length n of the numbers to be added is first specified. Then, the number of logical stages in the addition circuit is determined according to the above-defined criteria for a minimum-depth addition circuit. The required output drive strength of the addition circuit is established, and this defines the size of the logic gates requires to implement the nodes of the final stage. The size of the logic gates used to implement the nodes of the final stage determines the input capacitance of that stage. At this point, the design options available according to the configuration parameters of the present invention can be considered to provide a number of different options for the addition circuit. For each option or a selected group of these options, the capacitance of the spanning paths in the interconnection level to the final stage can be calculated. The choice of a spanning configuration in terms of the number of wires versus the extent of fan-out determines the size of logic gates at the driving level, which in turn determines the input capacitance as seen by the preceding level. Thus, a recursive design method is implemented to determine an optimum addition circuit for the application in hand.

[0076] The invention thus provides a number of different design options for addition circuits that allow a designer more freedom than has hitherto been the case in designing addition circuits.

[0077] Although representative embodiments of the invention have been illustrated and described, it will appreciated that various changes can be made therein without departing from the spirit and scope of the invention. Thus, the invention is to be limited by the scope of the claims that follow.

Claims

1. An addition circuit for adding together two binary numbers each having a length of n bits, comprising:

an array of logical nodes that are arranged so that each set of logical nodes extending widthwise of the circuit form a logical stage and each set of nodes extending depthwise of the circuits forms an addition path, with each pair of adjacent addition paths forming a column;

spanning paths arranged to interconnect selected logical nodes so that adjacent logical stages are connected via an interconnection level, each spanning path extending from a node in one stage across at least one column being connected to a number f of fan-out nodes in a subsequent stage, the circuit having the following configuration parameters:

i) for each interconnection level the number f of fan-out nodes lies in the range 1 to 2j, where j is the interconnection level index lying between 0 and m, 2j is the maximum fan-out number for that level, and there are m+2 logical stages;

ii) the fan-out f of nodes at each level is always no greater than the number f of fan-out nodes at a subsequent level;

iii) the number of columns across which a spanning path extends within an interconnection level is 2j; and

at least one level has a fan-out number f<2j and at least one level has a fan-out number f>1.

2. An addition circuit as claimed in claim 1 wherein for bit lengths n of a binary order the number (m+2) of logical stages is derived from the following equation:

n=2m+1.

3. An addition circuit according to claim 1 wherein for bit lengths n which are not binary orders, the number (m+2) of logical stages is derived from the following equation:

nbo=2m+1

where nbo is the next largest binary order after n.

4. An addition circuit according to claim 1 wherein each logical node receives at least two signals representing bits of the same significance (i) in the binary numbers to be added, and comprises at least one logic gate.

5. An addition circuit according to claim 1 wherein each spanning path conveys one or more signals from a node of one significance in one logical stage to a node of a different significance in a subsequent logical stage.

6. An addition circuit according to claim 1 wherein the fan-out f=1 for more than one level.

7. An addition circuit according to claim 6 wherein f=1 for all levels except the mth level.

8. An addition circuit according to claim 1 wherein at least one level has maximum fan-out (f=2j) where j=m.

9. An addition circuit according to claim 1 wherein the fan-out f=2 for at least two levels

10. A method of designing an addition circuit for adding together two binary numbers each of bit length n, the method comprising:

determining the number (m+2) of logical stages in the addition circuit according to the following:

for bit length n of a binary order, n=2m+1

and for bit lengths which are not binary orders nbo=2m+1 where nbo is the next largest binary order after n;

for each of said logical stages allocating a set of virtual nodes, said virtual nodes forming potential addition paths depthwise of the circuit and adjacent addition paths forming a column;

determining for each logical stage its expected input capacitance; and

defining spanning paths wherein the spanning paths constitute an interconnection level between adjacent logical stages, wherein definition of the spanning paths is carried out in accordance with the following configuration parameters and depending on the expected input capacitance of each stage:

i) for each interconnection level the number f of fan-out nodes in a subsequent stage to which a node of a preceding stage is connected lies in the range 1 to 2j, where j is the interconnection level index lying between 0 and m and 2j is the maximum fan-out number for that level,

ii) the fan-out f of nodes at each level is always no greater than the fan-out f of nodes at a subsequent level,

iii) the number of columns across which a spanning path extends within an interconnection level is 2j, and

at least one level has a fan-out number f<2j and at least one level has a fan-out number f>1.

11. An addition circuit for an integrated circuit, comprising:

a plurality of nodes, the nodes arranged in rows and columns, each row forming a logical stage, and each column forming an addition path;

a plurality of spanning paths connecting nodes in one column with nodes in one or more adjacent columns and in one or more subsequent stages; and

the number (m+2) of logical stages comprises:

for bit lengths n of a binary order, n=2m+1.

12. The circuit of claim 11 wherein the number (m+1) of stages further comprises:

for bit lengths n that are not binary orders, nbo=2m+1.

13. The circuit of claim 11 wherein spanning paths comprise metal lines arranged to interconnect selected nodes so that the adjacent logical stages are connected via an interconnection level, the circuit comprising the following configuration parameters:

i) for each interconnection level the number f of fan-out nodes lies in the range of 1 to 2j, where j is the interconnection level index lying between 0 and m, 2j is the maximum fan-out number for that level, and there are m+2 logical stages;

ii) the fan-out f of nodes at each level is always no greater than the number f of fan-out nodes at a subsequent level;

iii) the number of columns across which a spanning path extends within an interconnection level is 2j; and at least one level has a fan-out number f<2j and at least one level has a fan-out number f>1.

14. The circuit of claim 13 wherein the number (m+1) of stages comprises:

for bit lengths n that are not binary orders, nbo=2m+1.

15. The circuit of claim 14 wherein the plurality of spanning paths comprise metal lines, and wherein each node comprises at least one logic gate coupled to bits of the same significance in each operand by one or more metal wires.

16. A method for designing an addition circuit, comprising:

determining the bit-length n of the operands to be added;

determining the number (m+2) of logical stages in the addition circuits, comprising:

for bit length n of a binary order, n=2m+1;

determining the addition path for each operand bit to form one or more columns;

determining the expected input capacitance for each logical stage; and

defining a plurality of spanning paths connecting nodes in one column with one or more nodes in adjacent columns and in subsequent stages in accordance with the following configuration parameters:

i) for each interconnection level the number f of fan-out nodes in a subsequent stage to which a node of a preceding stage is connected lies in the range 1 to 2j, where j is the interconnection level index lying between 0 and m and 2j is the maximum fan-out number for that level,

ii) the fan-out f of nodes at each level is always no greater than the fan-out f of nodes at a subsequent level,

iii) the number of columns across which a spanning path extends within an interconnection level is 2j, and at least one level has a fan-out number f<2j and at least one level has a fan-out number f>1.

17. The method of claim 16 wherein determining the number of logical stages further comprises:

for bit lengths n that are not binary orders, nbo=2m+1 where nbo is the next largest binary order after n.

18. The method of claim 16 wherein determining the expected input capacitance comprises:

determining the required output drive strength of the addition circuit;

defining the size of the logic gates required to implement the nodes of the final stage; and

determining the input capacitance of the final stage.