Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

Abstract: A full adder is provided in which a sum logic circuit for producing the sum signal and a carry-out logic circuit for producing the carry-out output paths do not share internal nodes. In addition, the sum logic circuit and the carry-out logic circuit are both configured to obviate the need for transmission gates with respect to forming the sum signal and the carry-out signal.

Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

Abstract: Methods for compiling single-qubit quantum gates into braid representations for non-Abelian quasiparticles described by the Fibonacci anyon model are based on a probabilistically polynomial algorithm that, given a single-qubit unitary gate and a desired target precision, outputs a braid pattern that approximates the unitary to desired precision and has a length that is asymptotically optimal (for a circuit with such property). Single-qubit unitaries that can be implemented exactly by a Fibonacci anyon braid pattern are classified, and associated braid patterns are obtained using an iterative procedure. Target unitary gates that are not exactly representable as braid patterns are first approximated to a desired precision by a unitary that is exactly representable, then a braid pattern associated with the latter is obtained.

Abstract: A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.

Abstract: Systems, methods and media for implementing logic in the arithmetic/logic unit of a processor are disclosed. More particularly, hardware is disclosed for computing logical operations with minimal hardware by organizing the execution unit such that the propagate and generate functions required for the adder can be used as a basis to implement the bitwise logical instructions. The result of these functions is computed before execution of the instruction by an execution macro in the arithmetic/logic unit.

Abstract: In a full-adder of complementary carry logic voltage compensation, two input terminals of a first multiplexer are connected to a carry input and a carry inverted phase input respectively; an add signal is connected to a select signal; an input terminal of a first inverter is connected to an output signal of the first multiplexer. Two input terminals of a second multiplexer output an addend and a summand; an output signal of the first inverter is selected; an output terminal of the second multiplexer produces a carry signal; an input terminal of the second inverter is connected to an output signal of the second multiplexer for producing a carry inverted phase signal; two input terminals of a third multiplexer input the summand and carry inverted phase signal; an output signal of the first inverter is a select signal; and an output terminal of the third multiplexer produces a sum signal.

Abstract: A full-adder module (30) comprises a full-adder comprising a plurality of input and output terminals, a sum generation unit and a carry generation unit. The carry generation unit comprises a programmable inverter arranged to selectively invert a carry-in bit to the carry generating unit in response to a control signal applied to one of the input terminals. The full-adder module (30) provides an area-efficient logic block that supports signed multiplications, the logic block retaining its programmable nature and being capable of performing all the other operations it was intended to perform.

Abstract: A low power, high speed full adder cell is described. This cell supports all possible combinations of active high/active low input/output signal polarity (32 different combinations), without adding extra inverters or extra transistors. The cell makes liberal use of complementary metal oxide semiconductor (CMOS) transmission gates in order to minimize the number of transistors used, and to minimize their stacking. This significantly decreases the total transistor gate area consumed, resulting in minimal power dissipation and minimal cell size.

Abstract: A high speed low powered 4-2 compressor according to the present invention performs an XOR/XNOR operation of input data by using a single input type NAND/NOR logic circuit and a dual input type NAND/NOR logic circuit. Thus, delays to generate complementary signals are avoided. In addition, the 4-2 compressor uses a single railed multiplexer instead of a dual railed multiplexer, so that gate drive nodes and internal load capacitance are reduced. As a result, circuit area and power consumption of the 4-2 compressor are reduced.

Abstract: A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from a plurality of 4-input/1-output logical functions depending on configuration data. A 4-2 carry block generates a 4-2 carry output from the second to fourth logical inputs. A first signal is generated from at least the logical output, a second signal from at least the first logical input, a third signal from at least a 4-2 carry input signal, and a fourth signal from at least the 4-2 carry input signal. A multiplexer selects one of the second and third signals depending on the first signal to produce a carry output signal. An exclusive OR circuit produce an exclusive-ORed result from the logical output and the fourth signal.

Abstract: A method of designing an addition circuit, and an addition circuit designed according to the method are described. The design technique is optimised to facilitate design of an addition circuit of minimum depth. The design technique takes into account the number of logical stages of the addition circuit and the manner in which those stages are connected by spanning paths to create fan-out nodes. The number of fan-out nodes per level can be optimized. For bit lengths n, the number (m+2) of logical stages is n=2m+1 and for bit lengths n not of a binary order, the number (m+2) of logical stages is nbo=2m+1, where nbo is the next largest binary order after n.

Abstract: A parallel adder of the present invention operates at high speed and is reduced in size. The parallel adder outputs a carry signal from an inverter and a NAND-gate/NOR-gate to more rapidly generate the carry signal and selects a pass transistor after being passed through the NAND-gate/NOR-gate to reduce a layout surface. The parallel adder includes first and second full adders, each having a logic combination unit, a buffer, a carry output unit, an output controller unit and a sum output unit. The logic combination unit performs logical operations between input signals to generate a first control signal. The buffer inverts a carry input signal in accordance with the control of the logic combination unit, and the carry output unit generates a carry signal in accordance with the control of the logic combination unit to output the output signal from the buffer as a carry signal. The output controller logically combines the output signal from the logic combination unit and generates a second control signal.

Abstract: A double incrementing adder includes an AND gate configured to receive bits of the two input values of a common weight (“first weight”). The AND gate has an output terminal configured to carry the AND'ed bit. A three input XOR gate is configured to receive bits of the two input values of a common weight (“second weight”) one bit more significant than the first weight. The three input XOR gate is configured to XOR these values with the AND'ed bit to generate a three input XOR'ed bit.

Abstract: A programmable function block comprises a core logic circuit having a first argument input group consisting of first through fourth argument input terminals, a second argument input group consisting of first through fourth argument input terminals, first through third configuration input terminals, a core logic carry output terminal, a core logic carry generation output terminal, a core logic carry propagation output terminal, a ripple-core logic carry input terminal, and a sum output terminal. Connected to interconnection wires and the first and the second argument input groups, an input block includes eighth input selection units for selecting, as eight input selected signals, eight ones of signals on the interconnection wires, a fixed logic value of “1”, and a fixed logic value of “0”. Connected to the first through the third configuration input terminals, respectively, first through third memory circuits stores, as first through third stored logic values, a logic value of one bit.

Abstract: An MPEG-1 or an MPEG-2 motion compensation vector encoder circuit achieves smaller circuit area, and hence lower cost, by using circuitry, including ROMs, designed to implement residue arithmetic to calculate sum squared error in a parallel pipelined fashion. A residue-to-binary converter is implemented using distributed arithmetic and a reduction circuit that removes powers of two times the modulus M, both of which use carry save arithmetic operators. An improved ROM-accumulator, used in the residue-to-binary converter, is implemented using carry-save addition within the ROM-accumulator, and ripple-carry or carry-lookahead addition on the output of the ROM-accumulator.