HIGHLY LINEAR LOW VOLTAGE RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIER

Abstract

An operational amplifier circuit includes: a first differential pair 20 of a first conductivity type having a first current branch and a second current branch; a second differential pair 22 of a second conductivity type having a first current branch and a second current branch; a first current mirroring device MP11 and MP26 coupled between the first branch of the first differential pair 20 and the second branch of the second differential pair 22 for combining the currents from these two branches; and a second current mirroring device MN22 and M24 coupled between the first branch of the second differential pair 22 and the second branch of the first differential pair 20 for combining the currents from these two branches.

Description

FIELD OF THE INVENTION

[0001] This invention generally relates to electronic systems and in particular it relates to operational amplifiers.

SUMMARY OF THE INVENTION

[0002] An operational amplifier circuit includes: a first differential pair of a first conductivity type having a first current branch and a second current branch; a second differential pair of a second conductivity type having a first current branch and a second current branch; a first current mirroring device coupled between the first branch of the first differential pair and the second branch of the second differential pair for combining the currents from these two branches; and a second current mirroring device coupled between the first branch of the second differential pair and the second branch of the first differential pair for combining the currents from these two branches.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] In the drawings:

[0004] FIG. 1 is a schematic circuit diagram of a preferred embodiment highly linear rail-to-rail input/output operational amplifier stage;

[0005] FIG. 2 is a schematic circuit diagram of a more detailed example of the circuit of FIG. 1 including a bias generator and a startup circuit.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0006] A preferred embodiment highly linear rail-to-rail input/output operational amplifier stage that works for supply voltages less than 1 volt is shown in FIG. 1. This is highly suitable for voltage-follower operation in feedback loops of phase locked loops (PLLs) and delay locked loops (DLLs) in low voltage technologies.

[0007] The amplifier stage of FIG. 1 includes: PMOS transistors MPl, MP2, MP11, MP24, MP26, and MP27; NMOS transistors MN1, MN2, MN11, MN22, MN23, and MN24; current source I1 and I2; inputs VINM and VINP; and output OUT. The amplifier, shown in FIG. 1, has an input stage having rail-to-rail common mode range. This is made up of a pair of differential stages: an N-channel differential pair 20 and a P-channel differential pair 22 as shown in FIG. 1. The rail-to-rail output stage is made up of devices (transistors) MP24 and MN23. The mirroring devices (transistors) MP27 and MN11 determine the current in devices, MP24 and MN23, respectively.

[0008] The innovation in this design is due to the method employed for bringing in the currents into devices MP27 and MN11 as mirrored versions of the output currents in the dual differential input stages.

[0009] Focusing on the N-channel input pair 20, the drain current of transistor MN2 flows into transistor MP27 which is diode connected to mirror into transistor MP24. Similarly, the current out of transistor MN1 is mirrored through transistors MP11 and MP26 and fed into transistor MN11 to be mirrored into transistor MN23. It is assumed that transistors MP11 and MP26 are matched. The transistor pair MP27 and MP24, and transistor pair MN11 and MN23 can be ratioed (1:n) to the desired level. A similar mirroring arrangement is used for the currents out of the p-channel pair 22.

[0010] The important fact to note is that currents coming into transistors MP27 and MN11 are from one branch of each of the input pairs 20 and 22. This arrangement is much simpler than the typical prior art solutions (“An Easy-to-Design Rail-to-Rail CMOS Op-amp with High CMRR”, G. Klisnick and M. Redon, 1997 Int. Symp. on VLSI Tech., Sys. & App., pp. 62-64) and U.S. Pat. Nos. 5,337,008, Aug. 9, 1994 and 6,462,619, Oct. 8, 2002.

[0011] A complete schematic of the operational amplifier including a bias generator 40 and startup circuit 42 is shown in FIG. 2.

[0012] While this invention has been described with reference to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims

1. A circuit comprising:

a first differential pair of a first conductivity type having a first current branch and a second current branch;

a second differential pair of a second conductivity type having a first current branch and a second current branch;

a first current mirroring device coupled between the first branch of the first differential pair and the second branch of the second differential pair; and

a second current mirroring device coupled between the first branch of the second differential pair and the second branch of the first differential pair.

2. The circuit of claim 1 wherein the first differential pair is an N channel differential pair and the second differential pair is a P channel differential pair.

3. The circuit of claim 1 wherein the first current mirroring device comprises:

a first transistor coupled to the first branch of the first differential pair, the first transistor is diode connected; and

a second transistor coupled to the second branch of the second differential pair and having a control node coupled to a control node of the first transistor.

4. The circuit of claim 3 wherein the second current mirroring device comprises:

a third transistor coupled to the first branch of the second differential pair, the third transistor is diode connected; and

a fourth transistor coupled to the second branch of the first differential pair and having a control node coupled to a control node of the third transistor.

5. The circuit of claim 1 further comprising:

a third current mirroring device coupled between the second branch of the first differential pair and an output node; and

a fourth current mirroring device coupled between the second branch of the second differential pair and the output node.

6. The circuit of claim 5 wherein the third current mirroring device comprises:

a first transistor coupled to the second branch of the first differential pair, the first transistor is diode connected; and

a second transistor coupled to the output node and having a control node coupled to a control node of the first transistor.

7. The circuit of claim 6 wherein the fourth current mirroring device comprises:

a third transistor coupled to the second branch of the second differential pair, the third transistor is diode connected; and

a fourth transistor coupled to the output node and having a control node coupled to a control node of the third transistor.

8. The circuit of claim 1 further comprising:

a first differential input node coupled to a control node of the first branch of the first differential pair and to a control node of the first branch of the second differential pair; and

a second differential input node coupled to a control node of the second branch of the first differential pair and to a control node of the second branch of the second differential pair.

9. A method comprising:

providing a first current from a first branch of a first differential pair to a first node;

mirroring a second current from a second branch of the first differential pair into a second node;

providing a third current from a first branch of a second differential pair to the second node; and

mirroring a fourth current from a second branch of a second differential pair into the first node.

10. The method of claim 9 further comprising:

coupling a control node for the first branch of the first differential pair to a first input node;

coupling a control node for the first branch of the second differential pair to the first input node;

coupling a control node for the second branch of the first differential pair to a second input node; and

coupling a control node for the second branch of he second differential pair to the second input node.

11. The method of claim 9 wherein the first differential pair is N channel, and the second differential pair is P channel.

12. The method of claim 9 further comprising:

mirroring a current from the first node into an output node; and

mirroring a current from the second node into the output node.