Having Current Mirror Amplifier Patents (Class 330/257)
  • Patent number: 10185344
    Abstract: According to an aspect, a low-dropout (LDO) regulator includes a pre-charge buffer, an output stage, and a noise filter connected between the pre-charge buffer and the output stage of the LDO regulator. The noise filter includes a first resistor. The LDO regulator includes a transistor configured as an input to the output stage, and a compensation circuit connected to an input of the pre-charge buffer. The compensation circuit includes a second resistor. The compensation circuit is configured to provide a compensation current that produces a first voltage drop across the second resistor, where the first voltage drop offsets a second voltage drop produced by an input current of the transistor across the first resistor.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: January 22, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Petr Kadanka
  • Patent number: 10153742
    Abstract: An operational amplifier comprises: a first amplifier stage 4 comprising a first differential pair of transistors 8, 10 arranged to receive and amplify a differential input signal 18, 20 thereby providing a first differential output signal 22, 24; and a second amplifier stage 6 comprising a second differential pair of transistors 26, 28 arranged to receive and amplify the first differential output signal 22, 24 thereby providing a second differential output signal 38, 40.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: December 11, 2018
    Assignee: Nordic Semiconductor ASA
    Inventor: Phil Corbishley
  • Patent number: 10107895
    Abstract: A Radar Calibration Processor (“RCP”) for calibrating the amplitude of a stepped-chirp signal utilized by a synthetic aperture radar (“SAR”) is disclosed. The RCP includes a periodic amplitude error (“PAE”) calibrator, first non-periodic amplitude error (“NPAE”) calibrator in signal communication with the PAE calibrator, and a second NPAE calibrator in signal communication with the first NPAE calibrator.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: October 23, 2018
    Assignee: The Boeing Company
    Inventors: Kwang M. Cho, Kenneth W. Conte
  • Patent number: 10056892
    Abstract: A comparator circuit including: a first node and a second node, which receive a first current and a second current, respectively; a first current mirror, which includes a first load transistor and a first output transistor; and a second current mirror, which includes a second load transistor and a second output transistor.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 21, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Germano Nicollini, Roberto Modaffari
  • Patent number: 9977441
    Abstract: A device is configured to provide low dropout regulation. An amplifier stage includes a first transistor electrically connected to an output of the device, and a second transistor. A current mirror includes a third transistor electrically connected to the second transistor, and a fourth transistor electrically connected to the third transistor. The auxiliary current source has a control terminal electrically connected to a gate electrode of the fourth transistor. The pull down stage includes a fifth transistor having a gate electrode electrically connected to a drain electrode of the first transistor, and a sixth transistor having a gate electrode electrically connected to the gate electrode of the fourth transistor. The pull up transistor has a gate electrode electrically connected to a drain electrode of the fifth transistor. The first capacitor has a first terminal electrically connected to the gate electrode of the first transistor.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chung-Cheng Chou, Po-Hao Lee
  • Patent number: 9935598
    Abstract: An amplifying circuit comprises a differential input stage having a first input terminal, a second input terminal, and an intermediate node, wherein the differential input stage is configured to generate a differential current flowing through the intermediate node in response to an input voltage difference between the first and second input terminals. The amplifying circuit further comprises a first current source coupled to the intermediate node, which is configured to provide a first bias current which allows the differential current to vary within a predetermined range. The amplifying circuit further comprises an output terminal coupled to the intermediate node, and a second current source coupled to the intermediate node and configured to provide a second bias current. The second bias current compensates the differential current and the first bias current and produces an output current flowing through the output terminal in a predetermined direction. A measurement device is also described.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: April 3, 2018
    Assignee: Fluke Precision Measurement Ltd.
    Inventors: Hong Yao, Yong Yang, Hua Qui
  • Patent number: 9702911
    Abstract: A power sensor applies respective first and second currents having substantially equal magnitudes to a reference detector and a measurement detector that are thermally coupled to each other. The power sensor senses an input signal with the measurement detector, and it adjusts the respective magnitudes of the first and second currents by substantially equal amounts to correspondingly adjust a measurement characteristic of the measurement detector.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: July 11, 2017
    Assignee: Keysight Technologies, Inc.
    Inventors: Eric Breakenridge, Clive Robertson
  • Patent number: 9646536
    Abstract: A pixel circuit for an organic light emitting display includes first, second, third, fourth, fifth, and sixth MOS transistors, a first capacitor, and an organic light emitting diode. The gate electrode of the first MOS transistor receives a first scanning signal. The first electrode of the first MOS transistor receives a data signal. The gate electrode of the third MOS transistor receives a control signal. The gate electrode of the fourth MOS transistor receives the first scanning signal. The gate electrode of the fifth MOS transistor receives the control signal. The first electrode of the fifth MOS transistor receives a reference voltage. The gate electrode of the sixth MOS transistor receives a second scanning signal. The first electrode of the sixth MOS transistor receives the reference voltage.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: May 9, 2017
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Dong Qian, Gang Liu, Chen Liu
  • Patent number: 9625927
    Abstract: A drive circuit of the present invention, which drives a switching device in response to a control signal, includes: a current mirror circuit including an output transistor connected to a control electrode of the switching device and a reference transistor that is connected to the output transistor in a current mirror manner and supplies a mirror current to the output transistor; and a potential change circuit that is connected to the reference transistor and changes a control potential of the output transistor from a potential during mirror operation of the current mirror circuit.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: April 18, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Motoki Imanishi, Kenji Sakai, Takaki Nakashima
  • Patent number: 9614623
    Abstract: Methods and systems for replicating high bandwidth current outputs from a photodetector or another current source include using a transimpedance amplifier (TIA) to directly generate a TIA voltage that is linear with optical power at the photodetector. The TIA voltage is used to generate a current that flows to a log amp, which generates a voltage that is linear with the optical power in dB. Additionally, offset cancellation is used at the TIA and at the log amp.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: April 4, 2017
    Assignee: Fujitsu Limited
    Inventors: Noah Gottfried, Christopher Mesibov
  • Patent number: 9571101
    Abstract: According to one embodiment, a semiconductor device includes: a first circuit including a first transistor, a second transistor, the first and second transistors being capable of receiving first and second signals, respectively; a second circuit including a third transistor and a fourth transistor, a gate and one end of the third transistor being connected to one end of the first transistor, the fourth transistor being capable of receiving the first signal, one end of the fourth transistor being connected to the other end of the third transistor; and a third circuit configured to charge or discharge a node being connected to the one end of the first transistor according to the first signal.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: February 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Fumiya Watanabe, Mikihiko Ito, Masaru Koyanagi
  • Patent number: 9548707
    Abstract: Apparatus and method for an output stage of an amplifier are disclosed. A current source circuit provides current to a transistor connected to the amplifier output node to produce output voltage, and the current source circuit has two current mirror paths, one of which replicates the output voltage at the output node. As the output voltage approaches rail, more current is steered to the current mirror path not replicating the output voltage and provides additional current or voltage necessary to keep the current source circuit operational.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: January 17, 2017
    Assignee: Analog Devices, Inc.
    Inventor: Sukhjinder S. Deo
  • Patent number: 9438179
    Abstract: An amplifier apparatus includes a differential input pair, a current source, and a load. The differential input pair includes first and second transistors, and an auxiliary transistor. A control terminal of the first transistor receives a reference voltage. A first terminal of the second transistor is coupled to the first terminal of the first transistor, and a control terminal of the second transistor receives an input voltage. A first terminal of the auxiliary transistor is coupled to a first terminal of the first transistor, a second terminal of the auxiliary transistor is coupled to a second terminal of the first transistor, a control terminal of the auxiliary transistor receives a control voltage, and a base terminal thereof receives a power supply voltage. The current source and load are respectively coupled to the first terminals and second terminals of the first and second transistors.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: September 6, 2016
    Assignee: Intel Corporation
    Inventor: Yu-Chung Wang
  • Patent number: 9397624
    Abstract: A device includes an amplifier stage, a source follower, a resistive device, and a transistor. The source follower has an input terminal electrically coupled to an internal node of the amplifier stage, and an output terminal electrically coupled to an input terminal of the amplifier stage and an output terminal of the device. The resistive device has a first terminal electrically coupled to the output terminal of the device. The transistor is electrically coupled to a second terminal of the resistive device and the amplifier stage.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chung-Cheng Chou
  • Patent number: 9379672
    Abstract: A current amplifier is disclosed. The circuit has differential input and output and can be implemented in CMOS or bipolar integrated-circuit technologies. The input current is injected into a pair of primary branches, and is re-used at the output of the circuit without changing its natural flow, thus contributing to the overall current gain. A pair of secondary branches is connected to the primary branches in such a way as to provide currents proportional to the input currents according to a scaling factor dictated by the geometry of the transistors. The outputs of the secondary branches are cross-coupled relative to the outputs of the primary branches, in this way ensuring maximum current gain by the summing of the primary and secondary signal currents at the circuit output, without consuming additional DC power.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: June 28, 2016
    Assignee: Analog Devices, Inc.
    Inventor: Alexandru A. Ciubotaru
  • Patent number: 9356562
    Abstract: Operational transconductance amplifiers (OTAs) with enhanced slew rate are disclosed. An OTA can have a main amplifier and pre-amplifier gain stage to increase the effective transconductance and bandwidth of the OTA. The pre-amplifier and main amplifier can be coupled to enhance slew current without adding additional bias current to the main amplifier input stages. Pre-amplifier bias current can be recycled and redirected to the load. OTAs with enhanced slew rate can be particularly useful in applications requiring high-frequency switching of voltage levels to drive high capacitance lines. For example, an integrated touch sensor panel and display can be operated by alternatively applying a first voltage level to an electrode in a display mode and a second voltage level during a touch sensing mode using OTA sense or charge amplifiers with enhanced slew rate. Enhanced slew rate can increase the time available to demodulate a touch signal for improved system performance.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: May 31, 2016
    Assignee: Apple Inc.
    Inventor: A Motamed
  • Patent number: 9276531
    Abstract: Apparatus and methods for amplifier input protection are provided. In certain implementations, an amplifier input protection circuit includes a first JFET electrically connected between a first input and a first output, and a second JFET electrically connected between a second input and a second output. Additionally, a first clamp is electrically connected to the first output, and a second clamp is electrically connected to the second output. A first current mirror mirrors a current through the first clamp, and provides the mirrored current to a third JFET electrically connected between the first JFET's source and gate. Additionally, a second current mirror that mirrors a current through the second clamp, and provides the mirrored current to a fourth JFET that is electrically connected between a source and gate of the second JFET. Configuring the protection circuit in this manner can provide the benefits of both low noise and low fault current.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: March 1, 2016
    Assignee: Analog Devices, Inc.
    Inventors: Moshe Gerstenhaber, Rayal Johnson
  • Patent number: 9231570
    Abstract: A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: January 5, 2016
    Assignee: Solaredge Technologies Ltd.
    Inventor: Meir Gazit
  • Patent number: 9083295
    Abstract: The current feedback output circuit includes first and second transistors. The current feedback output circuit includes a current amplifier that has a non-inverting input terminal, an inverting input terminal, a first output terminal and a second output terminal, an input impedance of the non-inverting input terminal being higher than an input impedance of the inverting input terminal, and flows a current obtained by amplifying the difference between a current of an input signal to the non-inverting input terminal and a current input to the inverting input terminal between the first output terminal and the second output terminal. The current feedback output circuit includes first to sixth current mirror circuits. The current feedback output circuit includes a current feedback circuit that supplies a current responsive to a voltage at the signal output terminal to the inverting input terminal.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: July 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yamauchi, Hiroyuki Tsurumi
  • Patent number: 9052539
    Abstract: The present invention provides a liquid crystal display device, compensation circuit and TFT voltage shutdown method.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: June 9, 2015
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Poshen Lin, Yu Wu
  • Publication number: 20150130538
    Abstract: In one embodiment, a differential amplifier circuit includes a first input terminal, a second input terminal, a first transistor, a second transistor, a third transistor, a current source, a first output terminal, a second output terminal, a first passive element, and a second passive element. The first (second) transistor has a control terminal connected to the first (second) input terminal. The third transistor has a control terminal. The control terminal is applied predetermined bias voltage. The current source is connected to a first terminal in each of the first transistor, second transistor, and third transistor. The first (second) output terminal is connected to a second terminal of the first (second) transistor. The first (second) passive element is connected between the first (second) input terminal and the first (second) output terminal.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 14, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tetsuro ITAKURA, Masanori FURUTA, Shunsuke KIMURA, Go KAWATA, Hideyuki FUNAKI
  • Publication number: 20150130647
    Abstract: In one embodiment, a current amplifier circuit includes a first transistor, a first resistor, a second transistor, a second resistor, a first passive element, and a control circuit. The first transistor has a first terminal, a second terminal, and a control terminal. The first resistor has one end connected to the first terminal of the first transistor. The second transistor has a first terminal, a second terminal, and a control terminal. The second resistor has one end connected to the first terminal of the second transistor. The first passive element is connected between the first terminals of the first transistor and the second transistor. The control circuit controls at least one of voltage at the control terminals of the first transistor and the second transistor such that the voltage at the other end of the first resistor becomes equal to the voltage at the other end of the second resistor.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 14, 2015
    Inventors: Tetsuro ITAKURA, Masanori FURUTA, Akihide SAI, Junya MATSUNO, Yohei HATAKEYAMA
  • Patent number: 9030258
    Abstract: An amplifier circuit includes an input terminal and an output terminal. A current sinking transistor includes a first conduction terminal coupled to the output terminal and a second conduction terminal coupled to a reference supply node. A voltage sensing circuit has a first input coupled to the input terminal and a second input coupled to the output terminal. An output of the voltage sensing circuit is coupled to the control terminal of the current sinking transistor. The voltage sensing circuit functions to sense a rise in the voltage at the output terminal which exceeds the voltage at the input terminal, and respond thereto by activating the current sinking transistor.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: May 12, 2015
    Assignee: STMicroelectronics (Shenzhen) R&D Co., Ltd.
    Inventor: Yi Jun Duan
  • Patent number: 9019014
    Abstract: The programmable multi-gain current amplifier circuitry includes a pair of MOS transistors setting the voltage at X terminal to zero using negative feedback formed by a third MOS transistor. Input resistance is in the range of few tens of ohms. The input current ix, which is forced by the constant currents of the circuitry, is conveyed to the output port Z by source-coupling a complementary output pair of MOS transistors. Since this coupled pair is biased with a constant tail current, the drain current changes are equal but with opposite sign, regardless of their matching resulting in negative type CA with unity gain (iz=ix). Programmability is achieved utilizing the output stages. When a second differential pair is connected in parallel, it provides two additional current outputs. With the two differential pairs being biased with different tail currents (IT1 and IT2), the outputs are programmed by adjusting these tail currents.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: April 28, 2015
    Assignees: King Fahd University of Petroleum and Minerals, King Abdulaziz City for Science and Technology
    Inventor: Hussain Alzaher
  • Patent number: 9000844
    Abstract: Embodiments and methods herein operate as two-stage voltage controlled current sources (i.e., dynamic current sources) operating in class AB mode. Phase-delayed current injection circuits are associated with first-stage bias, second-stage bias, or both. The current injection circuits operate to quickly re-charge inter-stage parasitic capacitance associated with the active side of the class AB dynamic current source shortly after that side becomes inactive. Doing so quickly dissipates an otherwise slowly-decaying residual drive signal to prevent the output stage from continuing to conduct after the associated side of the current source becomes inactive. Excessive current consumption and possible destructive operation of the output stage are mitigated as a result.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: April 7, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Charles Parkhurst
  • Publication number: 20150091647
    Abstract: In an amplifier, a first stage receives a differential input voltage, which is formed by first and second input voltages, and outputs a first differential current in response thereto on first and second lines having respective first and second line voltages. A second stage receives the first and second line voltages and outputs a second differential current in response thereto on third and fourth lines having respective third and fourth line voltages. A third stage receives the third and fourth line voltages and outputs an output voltage in response thereto. A slew boost circuit detects a slew condition, in which a threshold difference arises between the first and second input voltages, and outputs a slew current in response thereto for maintaining a slew rate of the output voltage during the slew condition. The first stage includes circuits for reducing a variable difference between the first and second line voltages.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Vaibhav Kumar, Vadim Valerievich Ivanov
  • Patent number: 8994452
    Abstract: A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a wa
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: March 31, 2015
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tae Youn Kim, Robert Mark Englekirk, Dylan J. Kelly
  • Patent number: 8988402
    Abstract: An output circuit includes a differential amplifier circuit, an output amplifier circuit, a control circuit, input and output terminals, and first to third supply terminals applied with first to third supply voltages, respectively. The third supply voltage is set a voltage between the first and second supply voltages. The differential amplifier circuit differentially receives signals of the input and output terminals. The output amplifier circuit includes first and second transistors of different conduction type each other coupled in series between the first and third supply terminals via the output terminal, and having control terminals coupled to first and second output nodes of the differential amplifier circuit, respectively. The control circuit includes a third transistor and a switch, and controls the third transistor being in a diode coupling mode between the first supply terminal and the control terminal of the first transistor for a given period of the output period.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Tsuchi
  • Patent number: 8981798
    Abstract: An electronic system comprises a resistive sensor structure and an electronic circuit portion whose design is selected such that different resistive sensor structures may be combined within the same electronic circuit. To this end, the resistive sensor structure is used as a voltage/current converter that provides input currents to a current amplifier, which in turn provides an amplified output voltage on the basis of a difference of the input currents. The operating range of the current amplifier is adjusted on the basis of a programmable current source irrespective of the configuration of the resistive sensor structure.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: March 17, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventor: Antonino Scuderi
  • Patent number: 8975962
    Abstract: Embodiments of the invention are generally directed to improving the slew rate of an amplifier as the amplifier charges or discharges a capacitive load. In one embodiment, the amplifier is coupled to a slew-enhancing circuit which uses a control signal from the amplifier to aid the amplifier when charging or discharging the load. For example, the control signal may be an internal voltage used by the amplifier to control circuit elements within the amplifier. By routing the control signal to the slew-enhancing circuit, the control signal biases the circuit elements within the slew-enhancing circuit to source a boost current when charging the capacitive load or sink the boost current when discharging the capacitive load.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: March 10, 2015
    Assignee: Synaptics Incorporated
    Inventors: Eric Scott Bohannon, Marshall J Bell
  • Patent number: 8970301
    Abstract: Low power low noise input bias current compensation for an amplifier input stage is provided by recycling the tail current of the differential pair transistors. A local amplifier regulates the tail current and buffers the base current of the tail current transistor, which is mirrored back to the input transistors to provide input bias current compensation.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: March 3, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Rayal Johnson, Moshe Gerstenhaber
  • Patent number: 8970302
    Abstract: An operational amplifier includes a selective differential stage including a first current mirror and a current distribution circuit. First and second legs of the first current mirror are responsive to current in first and second paths of the current distribution circuit, which distributes a tail current in response to a first signal received by a first input of the operational amplifier. Current in a first path of a selection circuit in the second path of the current distribution circuit is responsive to a second signal received by a second input of the operational amplifier. Current in the second path of the selection circuit is responsive to a third signal received by a third input of the operational amplifier. An output stage generates an output signal responsive to a difference between the first signal and one of the second and third signals.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: March 3, 2015
    Assignee: Power Integrations, Inc.
    Inventor: Frank Joseph Schulz
  • Publication number: 20150035597
    Abstract: An operational amplifier includes a selective differential stage including a first current mirror and a current distribution circuit. First and second legs of the first current mirror are responsive to current in first and second paths of the current distribution circuit, which distributes a tail current in response to a first signal received by a first input of the operational amplifier. Current in a first path of a selection circuit in the second path of the current distribution circuit is responsive to a second signal received by a second input of the operational amplifier. Current in the second path of the selection circuit is responsive to a third signal received by a third input of the operational amplifier. An output stage generates an output signal responsive to a difference between the first signal and one of the second and third signals.
    Type: Application
    Filed: August 5, 2013
    Publication date: February 5, 2015
    Applicant: Power Integrations, Inc.
    Inventor: Frank Joseph Schulz
  • Publication number: 20150028954
    Abstract: A signal receiver includes a current source providing a current having a current value, a pair of active input devices, and a pair of resistors. Each active input device includes a control node, a first conduction node, and a second conduction node. One of the control nodes receives an input signal. The first conduction nodes are connected to each other and receive the current. One of the second conduction nodes serves as an output node. The active input devices output an output signal to a core circuit according to the current and the input signal. Each resistor has a resistance value. A target voltage value is determined according to the resistance value and the current value, such that a voltage swing of the output signal is limited within the target voltage value, and an operating voltage of the core circuit is substantially equal to the target voltage value.
    Type: Application
    Filed: July 24, 2014
    Publication date: January 29, 2015
    Inventors: Eer-Wen Tyan, Yu-Chieh Hung, Jian-Feng Shiu, Chao-An Chen
  • Publication number: 20150022267
    Abstract: Apparatus and methods for electronic amplification are provided. In one embodiment, an amplifier includes first and second input terminals, an amplification circuit, a feedback circuit, and a current mirror. The amplification circuit includes a non-inverting voltage input electrically connected to the first input terminal and to a bias voltage, an inverting voltage input electrically connected to the second input terminal, a voltage output, and a current output. The amplifier includes a first feedback path from the voltage output to the inverting voltage input through the feedback circuit and a second feedback path from the current output to the inverting voltage input through the current mirror, which can mirror a current from the current output to generate a mirrored current. A current source such as a transducer can provide an input current between the first and second input terminals, and the mirrored current can substantially match the input current.
    Type: Application
    Filed: July 16, 2013
    Publication date: January 22, 2015
    Inventor: Scott A. Wurcer
  • Publication number: 20150015334
    Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
    Type: Application
    Filed: September 29, 2014
    Publication date: January 15, 2015
    Inventors: Lawrence T. Clark, Scott E. Thompson
  • Publication number: 20150015333
    Abstract: An apparatus comprises a differential amplifier circuit and a current source. The differential amplifier circuit is configured to receive a voltage at an input, wherein the differential amplifier circuit generates an output voltage having a magnitude proportional to the received voltage over a voltage range to be measured at a specified output common mode voltage. The current source is electrically connected to an input of the differential amplifier circuit and is configured to subtract a midpoint of a voltage range of the battery voltage to be measured at the input of the differential amplifier, wherein a circuit supply voltage provided to the differential amplifier circuit and the current source is less than the voltage at the input.
    Type: Application
    Filed: May 30, 2014
    Publication date: January 15, 2015
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Hrvoje Jasa, Andrew M. Jordan
  • Publication number: 20140375386
    Abstract: The low-noise amplifier circuit exhibits reduced noise.
    Type: Application
    Filed: October 8, 2012
    Publication date: December 25, 2014
    Inventor: Frederic Rivoirard
  • Patent number: 8912849
    Abstract: An operation amplifier (op amp) having a bias current detection circuit that monitors the bias current flowing in an output stage of the op amp. When the bias current detection circuit detects that too much current is being wasted, e.g., sunk to ground, then the amount of bias current is reduced. Similarly, when the bias current detection circuit detects that insufficient bias current is being supplied to the output stage of the op amp, the amount of bias current is increased. In one implementation, the output of the bias current detection circuit may be signals indicative of, respectively, too much bias current and too little bias current, wherein those outputs are supplied to a state machine which is configured to control the amount of bias current being supplied in a stepwise fashion.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: December 16, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventor: Li-Wei Sheng
  • Patent number: 8913050
    Abstract: A plurality of transistors in which ratios of a channel length L to a channel width W, ?=W/L, are different from each other is provided in parallel as output side transistors 105a to 105c in a current mirror circuit 101 which amplifies a photocurrent of a photoelectric conversion device and an internal resistor is connected to each of the output side transistors 105a to 105c in series. The sum of currents which flow through the plurality of transistors and the internal resistor is output, whereby a transistor with large amount of ? can be driven in a linear range with low illuminance, and a transistor with small amount of ? can be driven in a linear range with high illuminance, so that applicable illuminance range of the photoelectric conversion device can be widened.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Shishido, Atsushi Hirose
  • Patent number: 8907725
    Abstract: Apparatus and methods for reducing load-induced non-linearity in amplifiers are provided. In certain implementations, an amplifier includes a current mirror, a buffer circuit, and an output stage. The buffer circuit can have a relatively high current gain and a voltage gain about equal to 1. The buffer circuit can amplify a mirrored current generated by the current mirror and provide the amplified mirrored current to the output stage, thereby helping to balance or equalize currents in the current mirror and avoiding the impact of load-induced offset error.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: December 9, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Moshe Gerstenhaber, Rayal Johnson
  • Patent number: 8903342
    Abstract: A high dynamic range precision variable amplitude controller includes a gain portion configured to apply a controllable amount of amplitude adjustment to an input signal. The gain portion includes two or more amplification stages each amplification stage having branches that are cross-coupled with branches of the other amplification stage. A control portion controls the current supply to the two or more amplification stages to control the amount of amplitude adjustment by the gain portion. The amplitude controller also includes a load portion that provides balanced impedances to the cross-coupled branches of the amplification stages throughout the amplitude control range.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: December 2, 2014
    Assignee: Rockwell Collins, Inc.
    Inventors: Russell D. Wyse, Michael L. Hageman
  • Patent number: 8896379
    Abstract: Provided is an error amplifier. The error amplifier includes: an amplifying unit receiving first and second input signals and amplifying a voltage difference between the received first and second input signals; a first voltage generating unit generating first and second driving voltages for driving the amplifying unit; a second voltage generating unit generating first and second body voltages to implement a body biasing method; a cascode current source including first to fourth PMOS transistors to provide a bias current to the amplifying unit and the first voltage generating unit; and an output unit outputting a signal of the voltage difference amplified by the amplifying unit, wherein the first and third PMOS transistors receive the first body voltage through a body terminal and the second and fourth PMOS transistors receive the second body voltage through a body terminal.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 25, 2014
    Assignees: Electronics and Telecommunications Research Institute, Industry-Academic Cooperation Foundation, Dankook University
    Inventors: Yil Suk Yang, Jongdae Kim, Yong-Seo Koo
  • Publication number: 20140340149
    Abstract: Low power low noise input bias current compensation for an amplifier input stage is provided by recycling the tail current of the differential pair transistors. A local amplifier regulates the tail current and buffers the base current of the tail current transistor, which is mirrored back to the input transistors to provide input bias current compensation.
    Type: Application
    Filed: May 20, 2013
    Publication date: November 20, 2014
    Applicant: Analog Devices, Inc.
    Inventors: Rayal Johnson, Moshe Gerstenhaber
  • Patent number: 8884604
    Abstract: A current mirror for generating a substantially identical current flow in two parallel current paths, each current path comprising a switching device and each switching device comprising first and second active terminals and a control terminal for controlling current flow between the first and second active terminals, the current mirror comprising a first switching device arranged such that its first active terminal is arranged to receive a first voltage, its second active terminal is arranged to receive a variable voltage that varies independently of the first voltage and its control terminal is arranged to receive a control voltage, a second switching device connected such that its first active terminal is arranged to receive the first voltage and its control terminal is arranged to receive the control voltage and a voltage control device connected to the second switching device such that an input of the voltage control device is connected to the second active terminal of the second switching device, the vo
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: November 11, 2014
    Assignee: Cambridge Silicon Radio Limited
    Inventor: Jens Bertolt Zolnhofer
  • Publication number: 20140292411
    Abstract: A class AB operational amplifier includes an input stage, an output stage and a level shifter stage to control the quiescent current of the output stage and to transfer the signal from the input stage to the output stage, and a control circuit of the level shifter stage. The control circuit includes a transistor differential pair having a differential input terminals and the differential voltage at the differential terminals of the differential pair controls the level shifter stage.
    Type: Application
    Filed: June 13, 2014
    Publication date: October 2, 2014
    Inventors: MarcoOrazio CAVALLARO, Serge RAMET, Tiziano CHIARILLO
  • Patent number: 8847684
    Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: September 30, 2014
    Assignee: SuVolta, Inc.
    Inventors: Lawrence T. Clark, Scott E. Thompson
  • Patent number: 8841970
    Abstract: Techniques for designing a transconductor configurable to have a low transconductance. In one aspect, a voltage to current conversion module is coupled to a 1:N current replication module. The voltage to current conversion module may be implemented as an operational amplifier configured with negative feedback to generate a current through a transistor, wherein such current is proportional to the difference between an input voltage and a common-mode reference. The 1:N current replication module is configured to mirror the generated current in another transistor, to a predetermined ratio, such that the output current is also proportional to the difference between the input voltage and the common-mode reference. In exemplary embodiments, the output stage driving the output current may be configured to operate as a Class A, Class B, or Class AB type amplifier.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: September 23, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Arash Mehrabi, Thurman S. Deyerle, IV, Guoqing Miao
  • Publication number: 20140266444
    Abstract: A power amplifier system with supply modulation mitigation circuitry and methods is disclosed. The power amplifier system includes a regulator having an unregulated input and a regulated output along with a power amplifier having a supply input for receiving a supply current from the regulated output and having a signal input and a signal output that comprise a main signal path. The supply modulation mitigation circuitry is adapted to sense a supply modulation signal output from the regulator, generate a cancellation signal that is a scaled inverse of the supply modulation signal, and inject the cancellation signal into a node within the power amplifier system to sum the supply modulation signal and cancellation signal together to reduce the supply modulation signal from within the main signal path.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 18, 2014
    Applicant: RF Micro Devices (Cayman Islands), Ltd.
    Inventors: Baker Scott, George Maxim
  • Patent number: 8836427
    Abstract: A folded cascode operational amplifier is disclosed. The folded cascode operational amplifier includes a first current source, a second current source, and a first voltage terminal connected to the first current source and the second current source. The folded cascode operational amplifier also includes a first input-transistor connected to the first current source in series, and a second input-transistor connected to the second current source in series. Further, the folded cascode operational amplifier includes a tail current source connected to a connection point between the first input-transistor and the second input-transistor, a load current source, and a second voltage terminal connected to the tail current source and the load current source. The folded cascode operational amplifier also includes an output-transistor connected to the load current source, and an output-terminal arranged between the second current source and the second input-transistor and connected to the output-transistor.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: September 16, 2014
    Assignees: CSMC Technologies FAB1 Co., Ltd., CSMC Technologies FAB2 Co., Ltd.
    Inventor: Liang Cheng