Abstract: The present disclosure discloses a sensing circuit and a source driver including the same, capable of decreasing influence on the performance of an integrator according to a panel load and reducing a chip area by excluding a feedback capacitor of the integrator. The sensing circuit may convert an input current, received from a display panel, into an output current having linearity and an amount of current smaller than the input current.

Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

Abstract: A highly linear time amplifier with power supply rejection. In a reset stage, the threshold value of an over-threshold detector is used for resetting an output node of an amplifier, to eliminate the impact of power supply voltage changes on the threshold value of the threshold detector. A node capacitor unit is charged under the control of an input clock signal. After completion of charging, the node capacitor unit is discharged under the control of a synchronous clock signal. The time amplification gain only depends on the proportion of the charge and discharge current, and the charging and discharging time are completely linear in principle, which eliminates the nonlinearity of the traditional time amplifier, and reduces the negative impact of threshold change on system performance.

Abstract: An amplifier includes a first input transistor, a second input transistor, a first cascode transistor, a second cascode transistor, a first current mirror circuit, and a second current mirror circuit. The first input transistor is coupled to a first input terminal. The second input transistor is coupled to a second input terminal and the first input transistor. The first cascode transistor is coupled to the first input transistor. The second cascode transistor is coupled to the second input transistor and the first cascode transistor. The first current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the first input terminal. The second current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the second input terminal.

Abstract: An ultrasonic imaging apparatus includes a plurality of transducers that transmit ultrasonic waves and a transmission unit that supplies drive signals to the plurality of transducers. An amplitude control voltage generation unit and a transmission circuit unit are connected to a common voltage power supply. An amplitude control voltage generation unit receives an output voltage of the voltage power supply and an attenuation degree setting signal instructing an attenuation degree of the drive signal for each of the transducers for weighting of the drive signal, and generates an amplitude control voltage corresponding to a voltage obtained by attenuating the output voltage by the attenuation degree. The output voltage of the voltage power supply is reduced to a voltage corresponding to the amplitude control voltage, and a drive signal having a predetermined waveform is generated whose amplitude is the voltage after the reduction for each of the transducers.

Abstract: A solid-state imaging element of the present disclosure includes: a pixel array in which a plurality of unit pixels is arranged in a matrix shape, the plurality of unit pixels each including a photoelectric conversion unit; and an analog-to-digital conversion unit that converts an analog pixel signal into a digital signal, the analog pixel signal being output from each of the plurality of unit pixels of the pixel array. Then, the analog-to-digital conversion unit includes a comparator that includes a differential input unit and an active load of the differential input unit, the differential input unit using, as an input, a prescribed reference signal and the analog pixel signal. At least one transistor that configures the active load includes a plurality of control terminals that controls current. The plurality of control terminals is electrically connected in common.

Abstract: An embodiment voltage-current converter circuit comprises a first amplifier and a second amplifier having homologous first input nodes configured to receive a voltage signal therebetween as well as homologous second input nodes having a resistor coupled therebetween. First and second current mirror circuits are provided comprising first input transistors having their control terminal coupled to the output nodes of the amplifiers. First and second current sensing circuitry having first and second current output nodes are coupled to the current mirror output nodes of the current mirror circuits and configured to provide therebetween a current which is a function of the voltage signal between the homologous first input nodes of the amplifier.

Abstract: A differential amplifier is provided. The differential amplifier includes: a differential input circuit, adjusting a second current and a third current flowing into the differential input circuit according to a first input voltage, a second input voltage, and a first current; a first current source circuit, generating the first current according to a first reference voltage; a current-mirror circuit, generating a fifth current according to a fourth current; a second current source circuit, generating a sixth current and a seventh current according to a second reference voltage; and an impedance circuit, coupled to the current-mirror circuit and a ground terminal, the differential amplifier having a low output voltage error.

Abstract: An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.

Abstract: An operational transconductance amplifier, that may include a first differential pair that comprises a first transistor and a second transistor that are coupled to each other at a certain node; wherein the first differential pair is configured to convert a differential input voltage to first and second output currents; a current source that is coupled to the certain node and may include an adjustable current sources; and a feedback unit that is coupled to the certain node and is configured to (a) receive the differential input voltage, and maintain a voltage of the certain node substantially fixed regardless of changes in the differential input voltage.

Abstract: A variable gain amplifier circuit is disclosed. In one embodiment, an amplifier circuit includes first and second stages. Each stage includes one or more inverter pairs, with one inverter of each pair coupled to receive an inverting component of a differential signal and the other inverter of the pair coupled to receive a non-inverting component. The first stage receives a differential input signal and produces an intermediate differential signal. The second stage receives the intermediate differential signal and produces a differential output signal, the differential output signal being an amplified version of the differential input signal.

Abstract: A transconductance circuit comprises a first transistor, a second transistor, a first source-degeneration device, a second source-degeneration device, a first feedback device, and a second feedback device. The gate node of the first transistor is coupled to a source node of the second transistor via the first feedback device. The gate node of the second transistor is coupled to a source node of the second transistor via the second feedback device. The source node of the first transistor is coupled to a reference voltage via the first source-degeneration device. The source node of the second transistor is coupled to the reference voltage via the second source-degeneration device.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that provide an apparatus comprising: a first transistor including a first gate, a first current terminal, and a second current terminal; a second transistor including a second gate, a third current terminal, and a fourth current terminal; the first current terminal coupled to the third current terminal; the first gate coupled to the second gate and the second current terminal; a third transistor including a third gate, a fifth current terminal, and a sixth current terminal, the fifth current terminal coupled to the second current terminal, third gate coupled to a voltage reference node; and a fourth transistor including a fourth gate, a seventh current terminal and an eighth current terminal, the seventh current terminal coupled to the sixth current terminal, the fourth gate coupled to the seventh current terminal and the eighth current terminal coupled to the fourth current terminal.

Abstract: A buffer stage includes a control circuit. The control circuit includes a voltage generator, a voltage-to-current converter, and a current-to-voltage converter. The voltage generator is configured to generate a compensation voltage. The voltage-to-current converter is configured to convert the compensation voltage into a compensation current. The current-to-voltage converter is configured to convert the compensation current into a recovery compensation voltage. The recovery compensation voltage is arranged for modifying an output voltage of the buffer stage.

Abstract: An instrumentation amplifier configured for providing high common mode rejection and low distortion is described and includes an input differential pair configured to receive a differential input voltage and differential feedback voltage and a folded cascode amplifying stage configured to receive output current mode signals provided from the input differential pair. A current mirror is configured to mirror output current mode signals provided from said folded cascode amplifying stage. An external gain setting configuration may include a resistor feedback network, which includes a first resistor being connected between feedback inputs of said input differential pair, a second resistor between an output terminal of the current mirror and a first feedback input of said input differential pair, a third resistor between a common terminal and a second feedback input of said input differential pair.

Abstract: The present invention is intended to provide constant drive conditions of a relay switch. A relay drive circuit includes a current mirror circuit, a current suppression circuit 26, and a transistor Q3. The current mirror circuit includes a transistor Q1, a first resistor element R1, a transistor Q2, and a second resistor element R2. A relay coil 18 is provided on a current supply path extending from a collector terminal of the transistor Q1 to an earth conductor. The current suppression circuit 26 includes a capacitor C1 as a current suppression element configured to suppress, after conduction between an emitter terminal and a collector terminal of the transistor Q2 has been made, the current flowing through the current suppression element itself as compared to that in such conduction.

Abstract: A multiple-gain transconductance amplifier circuit is presented. It is developed by utilizing programmable gain source-coupling differential pair output stage forming multiple-gain transconductance amplifier outputs. A reconfigurable nth-order filter based on a multi-gain transconductance amplifier where the multi-gain transconductance amplifier includes a linear voltage-to-current converter and a programmable current-folding output stage was implemented. The filter achieves independent programmability while still using a single active device per pole. Further, the proposed multiple-gain transconductance amplifier can be employed to design poly phase filters and transconductance amplifier cell for an amplifier-based low-dropout regulator.

Abstract: An input device associated with a sensing region is disclosed. The input device includes: a first sensor electrode associated with the sensing region and configured to propagate a resulting signal; an first auxiliary component configured to generate an output using a scaled signal; and a first impedance ratio-based current conveyor coupled to the first sensor electrode and including: a staging circuit configured to generate an input signal using the resulting signal and a ratio of a first impedance to a second impedance; and a set of current mirrors configured to generate the scaled signal from the input signal.

Abstract: In some embodiments, a Miller compensation and stabilization device for a feedback control loop includes a capacitor and a control circuit. The capacitor has a first terminal configured to be coupled to an output of a comparator of the feedback control loop and a second terminal. The control circuit is coupled to the second terminal of the capacitor and is configured to control, in response to a voltage applied to a setpoint input of the feedback control loop, a first voltage across the first and second terminals of the capacitor by controlling a value of a potential of the second terminal of the capacitor such that the first voltage is lower than a threshold.

Abstract: A power detector for use in an RF receiver. The detector includes a power reference generator and a power quantizer. The power reference generator develops a power reference current, voltage, or signal as a function of a power transferred via a received RF signal. The power quantizer is responsive to the power reference current, voltage, or signal to develop a digital field power value indicative of the power reference current, voltage, or signal.

Abstract: An amplifier includes a differential positive input, a differential negative input, and a transistor. The transistor is communicatively coupled to the differential positive input and differential negative input at a source of the transistor. The transistor is configured to track input common mode of the differential positive input and differential negative input.

Abstract: A voltage-to-current converter that reduces third harmonic distortion. An amplifier includes an input stage. The input stage includes a first voltage-to-current conversion stage and a second voltage-to-current conversion stage. The first voltage-to-current conversion stage is configured to provide an input to output gain with compressive nonlinearity. The second voltage-to-current stage is cascaded with the first voltage-to-current conversion stage. An input of the second voltage-to-current stage is connected to an output of the first voltage-to-current conversion stage. The second voltage-to-current conversion stage is configured to provide an input to output gain with expansive nonlinearity.

Abstract: In accordance with an embodiment of the present invention, a circuit includes a configurable clamp driver circuit for clamping a voltage at a gate terminal of a transistor below a turn-on voltage threshold upon switch-off of the transistor. In a first clamp driver circuit mode, an output terminal of the clamp driver circuit is configured to be coupled to the gate terminal of the transistor to provide a first discharge path from the gate terminal of the transistor upon switch-off of the transistor. In a second clamp driver circuit mode, the output terminal of the clamp driver circuit is configured to be coupled to an input terminal of a clamp circuit, wherein the clamp circuit is coupled to the gate terminal of the transistor to provide a second discharge path from the gate terminal of the transistor upon switch-off of the transistor.

Abstract: A device comprising includes an output terminal and a first current path from the output terminal to a first reference voltage. The first current path includes a series connection of current electrodes of a first transistor and a second transistor. The first transistor receives at a control electrode a signal to set a desired level of current to be conducted by the first current path. The second transistor generates at a control electrode a feedback signal indicative of an actual current conducted by the first transistor.

Abstract: An amplifier arrangement has an input transistor being connected between reference potential terminals by a current source and a current sink. An amplifier stage has an amplifier output coupled to a first connection node between the current sink and a first terminal of the input transistor by means of a feedback path, and an amplifier input connected to a second connection node between the current source and the second terminal of the input transistor. A level-shifting structure has a level-shifting element with one end connected to a reference connection, wherein the level-shifting element is adapted to perform a level-shifting of a potential at the second connection node with respect to a potential at the reference connection. The reference connection is coupled to one of the following: the amplifier output, the first connection node, a control terminal of the input transistor.

Abstract: According to an aspect, a low-dropout (LDO) regulator includes a pre-charge buffer, an output stage, and a noise filter connected between the pre-charge buffer and the output stage of the LDO regulator. The noise filter includes a first resistor. The LDO regulator includes a transistor configured as an input to the output stage, and a compensation circuit connected to an input of the pre-charge buffer. The compensation circuit includes a second resistor. The compensation circuit is configured to provide a compensation current that produces a first voltage drop across the second resistor, where the first voltage drop offsets a second voltage drop produced by an input current of the transistor across the first resistor.

Abstract: An operational amplifier comprises: a first amplifier stage 4 comprising a first differential pair of transistors 8, 10 arranged to receive and amplify a differential input signal 18, 20 thereby providing a first differential output signal 22, 24; and a second amplifier stage 6 comprising a second differential pair of transistors 26, 28 arranged to receive and amplify the first differential output signal 22, 24 thereby providing a second differential output signal 38, 40.

Abstract: A Radar Calibration Processor (“RCP”) for calibrating the amplitude of a stepped-chirp signal utilized by a synthetic aperture radar (“SAR”) is disclosed. The RCP includes a periodic amplitude error (“PAE”) calibrator, first non-periodic amplitude error (“NPAE”) calibrator in signal communication with the PAE calibrator, and a second NPAE calibrator in signal communication with the first NPAE calibrator.

Abstract: A comparator circuit including: a first node and a second node, which receive a first current and a second current, respectively; a first current mirror, which includes a first load transistor and a first output transistor; and a second current mirror, which includes a second load transistor and a second output transistor.

Abstract: A device is configured to provide low dropout regulation. An amplifier stage includes a first transistor electrically connected to an output of the device, and a second transistor. A current mirror includes a third transistor electrically connected to the second transistor, and a fourth transistor electrically connected to the third transistor. The auxiliary current source has a control terminal electrically connected to a gate electrode of the fourth transistor. The pull down stage includes a fifth transistor having a gate electrode electrically connected to a drain electrode of the first transistor, and a sixth transistor having a gate electrode electrically connected to the gate electrode of the fourth transistor. The pull up transistor has a gate electrode electrically connected to a drain electrode of the fifth transistor. The first capacitor has a first terminal electrically connected to the gate electrode of the first transistor.

Abstract: An amplifying circuit comprises a differential input stage having a first input terminal, a second input terminal, and an intermediate node, wherein the differential input stage is configured to generate a differential current flowing through the intermediate node in response to an input voltage difference between the first and second input terminals. The amplifying circuit further comprises a first current source coupled to the intermediate node, which is configured to provide a first bias current which allows the differential current to vary within a predetermined range. The amplifying circuit further comprises an output terminal coupled to the intermediate node, and a second current source coupled to the intermediate node and configured to provide a second bias current. The second bias current compensates the differential current and the first bias current and produces an output current flowing through the output terminal in a predetermined direction. A measurement device is also described.

Abstract: A power sensor applies respective first and second currents having substantially equal magnitudes to a reference detector and a measurement detector that are thermally coupled to each other. The power sensor senses an input signal with the measurement detector, and it adjusts the respective magnitudes of the first and second currents by substantially equal amounts to correspondingly adjust a measurement characteristic of the measurement detector.

Abstract: A pixel circuit for an organic light emitting display includes first, second, third, fourth, fifth, and sixth MOS transistors, a first capacitor, and an organic light emitting diode. The gate electrode of the first MOS transistor receives a first scanning signal. The first electrode of the first MOS transistor receives a data signal. The gate electrode of the third MOS transistor receives a control signal. The gate electrode of the fourth MOS transistor receives the first scanning signal. The gate electrode of the fifth MOS transistor receives the control signal. The first electrode of the fifth MOS transistor receives a reference voltage. The gate electrode of the sixth MOS transistor receives a second scanning signal. The first electrode of the sixth MOS transistor receives the reference voltage.

Abstract: A drive circuit of the present invention, which drives a switching device in response to a control signal, includes: a current mirror circuit including an output transistor connected to a control electrode of the switching device and a reference transistor that is connected to the output transistor in a current mirror manner and supplies a mirror current to the output transistor; and a potential change circuit that is connected to the reference transistor and changes a control potential of the output transistor from a potential during mirror operation of the current mirror circuit.

Abstract: Methods and systems for replicating high bandwidth current outputs from a photodetector or another current source include using a transimpedance amplifier (TIA) to directly generate a TIA voltage that is linear with optical power at the photodetector. The TIA voltage is used to generate a current that flows to a log amp, which generates a voltage that is linear with the optical power in dB. Additionally, offset cancellation is used at the TIA and at the log amp.

Abstract: According to one embodiment, a semiconductor device includes: a first circuit including a first transistor, a second transistor, the first and second transistors being capable of receiving first and second signals, respectively; a second circuit including a third transistor and a fourth transistor, a gate and one end of the third transistor being connected to one end of the first transistor, the fourth transistor being capable of receiving the first signal, one end of the fourth transistor being connected to the other end of the third transistor; and a third circuit configured to charge or discharge a node being connected to the one end of the first transistor according to the first signal.

Abstract: Apparatus and method for an output stage of an amplifier are disclosed. A current source circuit provides current to a transistor connected to the amplifier output node to produce output voltage, and the current source circuit has two current mirror paths, one of which replicates the output voltage at the output node. As the output voltage approaches rail, more current is steered to the current mirror path not replicating the output voltage and provides additional current or voltage necessary to keep the current source circuit operational.

Abstract: An amplifier apparatus includes a differential input pair, a current source, and a load. The differential input pair includes first and second transistors, and an auxiliary transistor. A control terminal of the first transistor receives a reference voltage. A first terminal of the second transistor is coupled to the first terminal of the first transistor, and a control terminal of the second transistor receives an input voltage. A first terminal of the auxiliary transistor is coupled to a first terminal of the first transistor, a second terminal of the auxiliary transistor is coupled to a second terminal of the first transistor, a control terminal of the auxiliary transistor receives a control voltage, and a base terminal thereof receives a power supply voltage. The current source and load are respectively coupled to the first terminals and second terminals of the first and second transistors.

Abstract: A device includes an amplifier stage, a source follower, a resistive device, and a transistor. The source follower has an input terminal electrically coupled to an internal node of the amplifier stage, and an output terminal electrically coupled to an input terminal of the amplifier stage and an output terminal of the device. The resistive device has a first terminal electrically coupled to the output terminal of the device. The transistor is electrically coupled to a second terminal of the resistive device and the amplifier stage.

Abstract: A current amplifier is disclosed. The circuit has differential input and output and can be implemented in CMOS or bipolar integrated-circuit technologies. The input current is injected into a pair of primary branches, and is re-used at the output of the circuit without changing its natural flow, thus contributing to the overall current gain. A pair of secondary branches is connected to the primary branches in such a way as to provide currents proportional to the input currents according to a scaling factor dictated by the geometry of the transistors. The outputs of the secondary branches are cross-coupled relative to the outputs of the primary branches, in this way ensuring maximum current gain by the summing of the primary and secondary signal currents at the circuit output, without consuming additional DC power.

Abstract: Operational transconductance amplifiers (OTAs) with enhanced slew rate are disclosed. An OTA can have a main amplifier and pre-amplifier gain stage to increase the effective transconductance and bandwidth of the OTA. The pre-amplifier and main amplifier can be coupled to enhance slew current without adding additional bias current to the main amplifier input stages. Pre-amplifier bias current can be recycled and redirected to the load. OTAs with enhanced slew rate can be particularly useful in applications requiring high-frequency switching of voltage levels to drive high capacitance lines. For example, an integrated touch sensor panel and display can be operated by alternatively applying a first voltage level to an electrode in a display mode and a second voltage level during a touch sensing mode using OTA sense or charge amplifiers with enhanced slew rate. Enhanced slew rate can increase the time available to demodulate a touch signal for improved system performance.

Abstract: Apparatus and methods for amplifier input protection are provided. In certain implementations, an amplifier input protection circuit includes a first JFET electrically connected between a first input and a first output, and a second JFET electrically connected between a second input and a second output. Additionally, a first clamp is electrically connected to the first output, and a second clamp is electrically connected to the second output. A first current mirror mirrors a current through the first clamp, and provides the mirrored current to a third JFET electrically connected between the first JFET's source and gate. Additionally, a second current mirror that mirrors a current through the second clamp, and provides the mirrored current to a fourth JFET that is electrically connected between a source and gate of the second JFET. Configuring the protection circuit in this manner can provide the benefits of both low noise and low fault current.

Abstract: A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate.

Abstract: The current feedback output circuit includes first and second transistors. The current feedback output circuit includes a current amplifier that has a non-inverting input terminal, an inverting input terminal, a first output terminal and a second output terminal, an input impedance of the non-inverting input terminal being higher than an input impedance of the inverting input terminal, and flows a current obtained by amplifying the difference between a current of an input signal to the non-inverting input terminal and a current input to the inverting input terminal between the first output terminal and the second output terminal. The current feedback output circuit includes first to sixth current mirror circuits. The current feedback output circuit includes a current feedback circuit that supplies a current responsive to a voltage at the signal output terminal to the inverting input terminal.

Abstract: The present invention provides a liquid crystal display device, compensation circuit and TFT voltage shutdown method.

Abstract: In one embodiment, a current amplifier circuit includes a first transistor, a first resistor, a second transistor, a second resistor, a first passive element, and a control circuit. The first transistor has a first terminal, a second terminal, and a control terminal. The first resistor has one end connected to the first terminal of the first transistor. The second transistor has a first terminal, a second terminal, and a control terminal. The second resistor has one end connected to the first terminal of the second transistor. The first passive element is connected between the first terminals of the first transistor and the second transistor. The control circuit controls at least one of voltage at the control terminals of the first transistor and the second transistor such that the voltage at the other end of the first resistor becomes equal to the voltage at the other end of the second resistor.

Abstract: In one embodiment, a differential amplifier circuit includes a first input terminal, a second input terminal, a first transistor, a second transistor, a third transistor, a current source, a first output terminal, a second output terminal, a first passive element, and a second passive element. The first (second) transistor has a control terminal connected to the first (second) input terminal. The third transistor has a control terminal. The control terminal is applied predetermined bias voltage. The current source is connected to a first terminal in each of the first transistor, second transistor, and third transistor. The first (second) output terminal is connected to a second terminal of the first (second) transistor. The first (second) passive element is connected between the first (second) input terminal and the first (second) output terminal.

Abstract: An amplifier circuit includes an input terminal and an output terminal. A current sinking transistor includes a first conduction terminal coupled to the output terminal and a second conduction terminal coupled to a reference supply node. A voltage sensing circuit has a first input coupled to the input terminal and a second input coupled to the output terminal. An output of the voltage sensing circuit is coupled to the control terminal of the current sinking transistor. The voltage sensing circuit functions to sense a rise in the voltage at the output terminal which exceeds the voltage at the input terminal, and respond thereto by activating the current sinking transistor.

Abstract: The programmable multi-gain current amplifier circuitry includes a pair of MOS transistors setting the voltage at X terminal to zero using negative feedback formed by a third MOS transistor. Input resistance is in the range of few tens of ohms. The input current ix, which is forced by the constant currents of the circuitry, is conveyed to the output port Z by source-coupling a complementary output pair of MOS transistors. Since this coupled pair is biased with a constant tail current, the drain current changes are equal but with opposite sign, regardless of their matching resulting in negative type CA with unity gain (iz=ix). Programmability is achieved utilizing the output stages. When a second differential pair is connected in parallel, it provides two additional current outputs. With the two differential pairs being biased with different tail currents (IT1 and IT2), the outputs are programmed by adjusting these tail currents.

Abstract: Embodiments and methods herein operate as two-stage voltage controlled current sources (i.e., dynamic current sources) operating in class AB mode. Phase-delayed current injection circuits are associated with first-stage bias, second-stage bias, or both. The current injection circuits operate to quickly re-charge inter-stage parasitic capacitance associated with the active side of the class AB dynamic current source shortly after that side becomes inactive. Doing so quickly dissipates an otherwise slowly-decaying residual drive signal to prevent the output stage from continuing to conduct after the associated side of the current source becomes inactive. Excessive current consumption and possible destructive operation of the output stage are mitigated as a result.