Method and apparatus for executing branch instructions of a stack-based program

Abstract

A method of executing a stack-based program containing branch instructions using a processor having a register-based architecture, the processor having means for implementing a stack using registers of the processor such that the processor may operate in a stack-based mode as well as a register-based mode, the method comprising the steps of: translating each branch instruction of the stack-based program into a branch instruction of a register-based program and including in the translated instruction an indication that the instruction relates to the stack-based operation mode; examining each translated branch instruction and, if the instruction includes said indication, updating a stack counter of said means for implementing a stack; and executing the branch instruction.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to a method and apparatus for executing branch instructions of a stack-based program and is applicable in particular, though not necessarily, to a method and apparatus for executing branch instructions of a Java Virtual Machine program using a RISC processor.

BACKGROUND OF THE INVENTION

[0002] The JAVA™ programming language was developed by Sun Microsystems™ as a means of creating highly compact program code which can be executed on virtually any processing system. Whilst Java programs are translated into programs for a so-called Java Virtual Machine (JVM), and since the JVM can be implemented on any processor system, JAVA is effectively system independent.

[0003] JVM is an example of a stack-based instruction set architecture—other examples of stack based architectures are the MULTOS virtual machine and the Visual Basic virtual machine. Stack-based languages are designed to operate on processors (real or virtual) which temporarily store data, during the execution of a program instruction (or series of instructions), in a stack, i.e. which utilise a stack-based architecture. Data is added to or removed from the top of the stack as appropriate. The location of stack data to be acted upon by an instruction, or the stack location at which the result is to be stored, is implicit in the instruction. For example, the JVM instruction “iadd” requires the removal of the top two elements of the stack, and their replacement with the result of the addition on the top of the stack. Stack-based architectures are therefore fundamentally different from the register-based architectures of most modern microprocessors and which use a large bank of registers to temporarily store data during execution of program instructions. An example of an instruction used belonging to a register based programming language is “add rx,ry,rz”, which requires that the contents of registers ry and rz be added together, and the result stored in register rx. It will be apparent that the stack-based language architecture results in a much more compact program code than the register-based architecture.

[0004] This said, a JVM is more often than not implemented on a microprocessor having a register-based architecture. This requires the translation (static or dynamic) of the JVM program to be executed, into the register-based programming language used by the microprocessor. Broadly speaking, two translation strategies have been adopted: software-only solutions and hardware accelerators.

[0005] Software acceleration of Java involves the use of Just In Time (JIT) techniques. In the JIT approach, the machine-independent Java bytecodes are translated before execution into the native machine instructions of the host platform. JIT techniques (and their derivatives, such as HotSpot™ from Sun Microsystems) have proven to be useful on large platforms (e.g. the Intel Pentium™ processor and its equivalents) where processing power and memory are available in abundance. In embedded systems (using for example RISC processors such as the ARM™ and ARC™ processor families), the use of JIT technology suffers from several drawbacks:

[0006] The JIT compiler has to be a part of the application run-time. This component is typically quite complex (it is after all a compiler back-end) and requires considerable resources, which are often not available in low-cost embedded systems.

[0007] The use of highly optimizing JIT schemes may introduce security holes into the virtual machine. This is unacceptable in security-conscious applications (such as smartcards).

[0008] JIT compiled code suffers from what is termed code bloat. This means that the size of the native code produced by the JIT compiler is often up to five times larger than the size of the original JVM bytecodes.

[0009] Because the JIT phase is time consuming, larger Java applications suffer from noticable (and annoying) start-up times. The processor cycles used to JIT compile Java classes use up valuable battery power, and this fact may exclude this implementation approach from many battery-powered application areas.

[0010] RISC processors therefore tend to make use of a hardware coprocessor module which adds an extra pipeline stage to the main processor, and which converts stack-based instructions “on-the-fly” into native register-based program instructions. These coprocessors are typically quite large in terms of their component count (duplicating much of the hardware components contained in the RISC processor, such as the program fetch logic) and are comparable in size to the main processor itself. This of course adds to the cost of the processor. Coprocessors also tend to introduce a degree of inflexibility, only being operable with one particular “flavour” of JVM.

[0011] In architectures which make use of a hardware coprocessor, the coprocessor is activated by means of executing a mode switch instruction contained within a program, and which switches the processor into a special mode (“Java mode” in the case of Java accelerators). In this mode, the main processor fetch unit is disabled, and replaced by the “stack mode” fetch unit. This fetch unit retrieves a stack-based instruction (e.g. JVM instruction) from the program memory, translates it into a sequence of native instructions (e.g. RISC) of the main processor, and passes the translated sequence of instructions down the RISC processor pipeline.

[0012] A stack-based program will typically contain (short) sequences of code which may be efficiently translated into one line or a reduced number of lines of the register-based program code, i.e. as opposed to translating the sequences line by line. The process of identifying and translating such sequences may be carried out by the program loader (typically software executed by the register processor) which loads the stack-based code into the program memory prior to executing the program. The result will be a sequence of code which contains both stack-based code and register-based code interleaved. Special instruction can be included to identify the former. When the coprocessor architecture is used, the coprocessor is switched on when a block of stack based instructions is to be executed and is switched off when a block of register-based instructions is to be executed. However, as each mode switch can consume many clock cycles, the advantages obtained by identifying and translating such code blocks are to a great extent negated because the overhead of the mode switch operation is greater than the savings provided by using an optimised version of the code.

[0013] A more efficient approach to executing stack-based programs on a register-based architecture will be described in more detail later. However, the essence of the approach is the assignment of a part (typically 16 registers, r0 to r15) of the general-purpose register bank of the register-based (e.g. RISC) processor to act as a stack, and adding new instructions to the processor which allow stack operations to be performed using the designated part of the register bank. The new instructions are differentiated from existing instructions by the inclusion therein of suitable indicators (nb. the instructions are not new per se, rather, by the inclusion of the indicators, the instructions can be interpreted in a new way).

[0014] For certain stack-based instructions, these indicators may be one of three phantom registers, called here r0+, r1− and r1—(these phantom registers are identified by register addresses corresponding to three unused registers of the available registers). Translation circuits include phantom register addresses in translated instructions when appropriate. Whenever a register mapping circuit detects one of the phantom register addresses in an instruction, it:

[0015] a) substitutes 0 for r0+, and 1 for r1− and r1—, and

[0016] b) sends a control signal to increment a 4-bit stack counter (SC) by one for r0+, decrement SC by one for r1− and decrement SC by two for r1—.

[0017] In this way, the structure of the stack is dynamically maintained.

STATEMENT OF THE INVENTION

[0018] The structure of the JVM instruction set requires the frequent use of so-called “conditional branch” instructions in JVM programs. A conditional branch instruction has the form if <condition>is true then branch to <address>. For example, the JVM instruction ifne pops the top element from the stack, compares it to zero, and branches to a specified address if the value of the element is not zero. The JVM instruction if_icmpne pops the top two elements from the stack, and branches to the specified address if the values of the two elements are not equal.

[0019] Using the approach outlined above, and considering the ARC instruction set, the JVM instruction ifne<lab> could be translated as:

[0020] sub.f r1, r1—, 0

[0021] br.nz <lab>

[0022] where the inclusion of the register address r1—in the first instruction identifies the instruction as one to be executed using the stack-based mode (r1—will be replaced by r1, with the stack counter SC being subsequently decremented by 2). The ARC branch instruction contains a set of 5 bits (referred to as Q bits) which define the condition upon which branching is to occur. Following execution of the first (sub) instruction, a set of 5 corresponding bits in a flag register are set. The Q bits of the branch instruction are compared with the 5 flag bits to determine whether or not branching is to occur. Unfortunately, the need for two instructions in the register-based programming code expands the size of the code segment (from 3 to 8 bytes), and has a negative impact on execution time.

[0023] According to a first aspect of the present invention there is provided a method of executing a stack-based program containing branch instructions using a processor having a register-based architecture, the processor having means for implementing a stack using registers of the processor such that the processor may operate in a stack-based mode as well as a register-based mode, the method comprising the steps of:

[0024] translating each branch instruction of the stack-based program into a branch instruction of a register-based program and including in the translated instruction an indication that the instruction relates to the stack-based operation mode;

[0025] examining each translated branch instruction and, if the instruction includes said indication, updating a stack counter of said means for implementing a stack, and executing the branch instruction.

[0026] It will be appreciated that the stack counter may be updated before, during, or after execution the branch instruction.

[0027] Embodiments of the present invention offer the significant advantage that a stack-based branch instruction can be translated into a single register-based branch instruction. This reduces the size of the translated code, and reduces the instruction execution time.

[0028] Typically, each register-based branch instruction contains a set of condition flags which define the condition on which branching is to occur. Preferably, said indication that an instruction relates to the stack-based operation mode is contained in the condition flags. More preferably, said indication is contained in one of the flags.

[0029] Preferably, the translation of stack-based instructions, including branching instructions, fetched from the program memory is carried out prior to execution of the program. The translated program is stored temporarily in memory. As the code expansion resulting from the translation is less than that resulting from the use of a hardware coprocessor, the memory requirements are not excessive. Alternatively, the translation of stack-based instructions fetched from the program memory may be carried out on-the-fly, i.e. immediately prior to the execution of the instructions. This avoids the need for a large memory to store expanded register-based instructions.

[0030] In one embodiment of the invention, the stack based-program is a JVM program, and the processor having a register-based architecture is a RISC processor such that the register-based instructions are RISC instructions. However it will be appreciated that the invention may also be applied to other stack-based programming languages and other processor architectures.

[0031] According to a second aspect of the present invention there is provided a register-based processor system comprising:

[0032] a processor core having a plurality of registers and a stack counter arranged to facilitate access to a stack formed using said registers, the processor being arranged to execute register-based instructions;

[0033] a translation mechanism arranged to fetch stack-based instructions and to translate the fetched instructions into register-based instructions, the translation mechanism comprising means for recognising a branch instruction in the fetched instructions and to include in the corresponding translated instruction an indication that the instruction relates to a stack-based mode of operation; and

[0034] means for identifying translated instructions containing said indication and for updating said stack counter in response.

[0035] In certain embodiments of the invention, said translation mechanism comprises a set of software instructions which are executed by the processor core. In other embodiments, the translation mechanism comprises circuitry coupled to an input of the processor core. In yet other embodiments, the translation mechanism comprises both software and hardware components.

[0036] Preferably, the translation mechanism is arranged to set a flag bit of a translated branch instruction to provide said indication that the instruction relates to a stack-based mode of operation.

[0037] Preferably, said means for identifying translated instructions containing said indication comprises a circuit coupled to the input of the processor core which tests a flag bit of a translated branch instruction to determine if that instruction is to be executed using the stack-based mode. If the flag bit indicates that the instruction is to be executed using the stack-based mode, the means updates the stack counter, and resets the flag bit before passing the instruction to the processor core for execution.

[0038] Preferably, said circuit receives as an additional input a flag bit which can have one of two values. If the flag bit is set to a first value, the stack-based mode is switched on and the circuit operates as described. If the flag bit is set to the second value, the stack-based mode is switched off and the operation of the circuit is inhibited. The flag bit may be set dynamically.

[0039] The processor core may be a RISC processor core, e.g. an ARM™ or ARC™ processor core.

BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG. 1 illustrates schematically a modified RISC processor system for executing a JVM program;

[0041] FIG. 2 illustrates schematically a part of the RISC processor system of FIG. 1 in more detail;

[0042] FIG. 3 illustrates in more detail register address adaption circuitry of the processor system part shown in FIG. 3;

[0043] FIG. 4 illustrates schematically a part of the RISC processor system of FIG. 1 designed to handle branching instructions; and

[0044] FIG. 5 is a flow diagram illustrating a method of executing branching instructions of a JVM program on a RISC processor system.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

[0045] The technique of efficiently executing stack-based programs on an extended RISC architecture uses the following modules arranged at the input side of the processor core:

[0046] A buffer (BUF) which holds a block of stack-based instructions. The buffer may be implemented in hardware or software.

[0047] A circuit or software module (TR1) which replaces (translates) a single stack-based instruction with one or more native RISC+ instructions.

[0048] A circuit or software module (TR2), which compares a sequence of stack-based instructions with a collection of patterns stored in the module, and replaces (translates) any matching stack-based sequence with a one or more native RISC+ instructions which are also stored in the module.

[0049] A circuit or software module (DET) which detects that no pattern stored in the module corresponds to the current input sequence, and generates a control signal which activates the module TR1 to replace (translate) each individual stack-based instruction in the sequence with its corresponding native RISC+ instruction.

[0050] FIG. 1 shows the arrangement of these modules to implement a technique for efficiently executing stack-based programs 100 on an augmented RISC architecture 106. The stream of stack-based instructions is fed into the BUF module 101. The contents of the buffer are examined by the DET module 102, which determines whether the instruction code sequence matches any of the patterns stored in the TR2 module 104. If no match is detected, the instructions in the BUF module are translated individually into native RISC+ instructions by the TR1 module 103 and are passed to the fetch unit of the processor. (From the following discussion, it will be clear that the translation process carried out by TR1 103 is relatively simple as the translated instructions preserve much of the stack related information contained in the stack-based instructions. Translation can be carried out using a simple look-up table) If a match is detected, the output sequence of native RISC+ instructions, stored in TR2 104, is passed to the fetch unit 105 of the processor.

[0051] By way of example, consider the following sequence of stack-based (JVM) instructions representing the simple operation x=x+y: 1 iload x ; Load local variable x onto the stack iload y ; Load local variable y onto the stack iadd ; Add top stack elements and replace with result istore x ; Store result in local variable x

[0052] The TR1 module could translate individual JVM instructions into respective native RISC+ instructions. An example translation scheme for the instructions in the above fragment is shown below (where rn identifies a register of the simulated stack when 0<=n=>5): 2 iload x => mov r0+,rx iload y => mov r0+,ry iadd => add r2,r1−,r2 istore x => mov rx,r1−

[0053] However, a pattern consisting of two loads from local variables, followed by an arithmetic operation, followed by a store to a local variable, is stored in the TR2 module. The DET module detects this pattern in the input block, inhibits module TR1, and causes TR2 to output an optimised RISC instruction in place of the instructions which would be individually translated by TR1. This optimised RISC instruction is:

[0054] add rx,rx,ry.

[0055] In order to implement stack-like operations within the existing RISC instruction set, some means must be provided to control the operation of a stack counter control circuit For this purpose, the concept of a phantom register is introduced. In addition, a special mechanism is provided to handle branch instructions. However, this mechanism will be considered later, and the concept of the phantom register is first considered.

[0056] A phantom register is a register number which is an alias for stack register number 0 or 1, and is used by the register mapping mechanism to specify how the stack counter is to change after performing the mapping. Three phantom registers are required to implement a stack-based instruction set extension, called r0+, r1− and r1—(these phantom registers are identified by register addresses corresponding to three unused registers of the 64 available registers). The translation circuits TR1 and TR2 include phantom register addresses in translated instructions when appropriate. Whenever the register mapping circuit detects one of the phantom register addresses in an instruction, it:

[0057] a) substitutes 0 for r0+, and 1 for r1− and r1—, and

[0058] b) sends a control signal to increment a 4-bit stack counter (SC) by one for r0+, decrement SC by one for r1− and decrement SC by two for r1—.

[0059] If none of the three operands (A,B or C) is a phantom register address, the register mapping circuit sends a control signal to leave SC unchanged.

[0060] Some examples of implementing stack-based instructions using the augmented RISC instruction set are shown below. With the register mapping circuit enabled, the first “empty” slot on the stack is mapped via register number 0, the top of stack element on the stack via register number 1, the second stack element via register number 2 and so on.

[0061] To add the two top stack elements and replace them with their sum:

[0062] add r2,r1−,r2.

[0063] The second stack element is replaced with the sum of the top of stack element and the second stack element. Since phantom register r1− is used, the stack counter register will be decremented by 1 after executing the instruction. This will cause the old second stack element to become the new top of stack element when the subsequent instruction is executed.

[0064] To duplicate the top stack element:

[0065] mov r0+,r1

[0066] The first empty slot on the stack is filled with the top stack element. Since phantom register r0+ is used, the stack counter register will be incremented by 1 after executing the instruction. This will cause the old first empty slot to become the new top of stack element when the subsequent instruction is executed.

[0067] To load a constant on top of the stack:

[0068] mov r0+,#13.

[0069] As has already been mentioned, a special mechanism is provided to handle branch instructions. This mechanism relies upon the setting in branch instructions translated by TR1, of one of a set of condition flags to indicate that the instruction relates to a stack-based mode of operation. According to the RISC+ model proposed here, and in particular when applied to the ARC™ processor core, a RISC branch instruction has the form: 3 Instruction field jump to address condition flags (Q)

[0070] The four least significant bits of five Q bits are used to define the following six branching conditions:

[0071] SZ—stack top zero

[0072] SNZ—stack top non zero

[0073] SGZ—stack top greater than zero

[0074] SLZ—stack top less than zero

[0075] SGEZ—stack top greater or equal zero

[0076] SLEZ—stack top less than or equal to zero

[0077] This leaves one “spare” bit which is used here to indicate that the branch instruction relates to a stack-based operating mode of the RISC+ processor. A hardware modification is made to the processor core to detect this bit and to update the stack counter accordingly. This scheme allows the single operand ifxx instructions to be mapped into a single RISC+ instruction.

DETAILED EXAMPLE

[0078] As an example of a preferred embodiment of the technique, translation schemes TR1 and TR2 for an augmented version of ARC™ RISC core and an integer subset of JVM instructions will now be described.

[0079] Translation Scheme TR1

[0080] As described above, this module (implemented in hardware or software) translates a JVM bytecode into a sequence of one or more RISC+ instructions. The following description lists the mnemonic of the JVM bytecode to the left, and its corresponding RISC+ translation to the right of the arrow (=>). A unified data/local variable stack is assumed. The identifier r<x> refers to the location of variable <x> within the stack (relative to the top of stack).

[0081] a. Push a constant on stack 4 aconst_null => mov r0+,0 iconst_m1 => mov r0+,−1 iconst_0 => mov r0+,0 iconst_1 => mov r0+,1 iconst_2 => mov r0+,2 iconst_3 => mov r0+,3 iconst_4 => mov r0+,4 iconst_5 => mov r0+,5 bipush n => mov r0+,n sipush n => mov r0+,n

[0082] b. Load a local variable on the stack 5 iload <x> => mov r0+,r<x> iload_0 => mov r0+,r<0> iload_1 => mov r0+,r<1> iload_2 => mov r0+,r<2> iload_3 => mov r0+,r<3>

[0083] c. Store a value from the stack into a local variable 6 istore <x> => mov r<x>,r1− istore_0 => mov r<0>,r1− istore_1 => mov r<1>,r1− istore_2 => mov r<2>,r1− istore_3 => mov r<3>,r1−

[0084] d. Generic stack manipulation operations 7 nop => nop pop => mov r1,r1− pop2 => mov r1,r1− mov r1,r1− dup => mov r0+,r1 swap => mov r0,r1 mov r1,r2 mov r2,r0 dup_x1 => mov r0+,r2 dup_x2 => mov r0,r1 mov r1,r2 mov r2,r3 mov r3,r0+ dup2 => mov r0+,r2 mov r0+,r2 dup2_x1 => mov r0+,r2 mov r0+,r2 mov r3,r5 mov r4,r1 mov r5,r2 dup2_x2 => mov r0+,r2 mov r0+,r2 mov r3,r5 mov r4,r6 mov r5,r1 mov r6,r2

[0085] e. Integer arithmetic and boolean 8 iadd => add r2,r2,r1− isub => sub r2,r2,r1− ineg => sub r1,0,r1 iinc <x>,n => add r<n>,r<n>,n iand => and r2,r2,r1− ior => or r2,r2,r1− ixor => xor r2,r2,r1−

[0086] To illustrate the handling of branch instructions by TR1, the following examples are given.

[0087] The JVM sequence:

[0088] iload x

[0089] ifne lab

[0090] can be translated into

[0091] mov.f r0+,rx

[0092] br.snz lab

[0093] The sequence

[0094] iload x

[0095] biconst 20

[0096] iadd

[0097] ifge lab

[0098] can be translated into

[0099] mov.f r0+,rx

[0100] mov.f r0+,20

[0101] add.f r2,r1−,r2

[0102] br.sgez lab

[0103] Translation Scheme TR2

[0104] A partial definition of translation scheme TR2 is shown below. The name <bop> refers to any JVM binary integer operation code and <uop> refers to any JVM unary integer operation. The left hand side is the JVM sequence to be matched and the (optimised) RISC+ instruction equivalent is shown to the right of the arrow (=>).

[0105] a) Pattern 1 9 iload <x> iload <y> <bop> istore <z> => <bop> r<z>,r<x>,r<y>

[0106] b) Pattern 2 10 iload <x> iload <y> <bop> => <bop> r0+,r<x>,r<y>

[0107] c) Pattern 3 11 iload <x> biconst n <bop> istore <y> => <bop> r<y>,r<x>,n

[0108] d) Pattern 4 12 iload <x> biconst n <bop> => <bop> r0+,r<x>,n

[0109] e) Pattern 5 13 iload <x> <uop> istore <x> => <uop> r<x>,r<x>

[0110] f) Pattern 6 14 iload <x> istore <y> => mov r<y>,r<x>

[0111] g) Pattern 7 15 biconst n istore x => mov r<x>,n

[0112] The handling of branch instructions is illustrated by the following example.

[0113] The conditional statement in Java:

[0114] if(x>y) { . . . }

[0115] translates to the following JVM bytecode:

[0116] iload x

[0117] iload y

[0118] if_icmple lab

[0119] This can be translated (assuming variables x and y are in the “window”) into:

[0120] sub.f r0,rx,ry

[0121] br.le lab

[0122] The person of skill in the art will appreciate that many similar patterns may be produced.

[0123] In order to exploit the large register bank of the ARC and the powerful three-operand instructions, the present approach adopts a unified operand/local variable stack, mapped into the first 16 registers of the ARC register bank. Each JVM method definition in a class file contains information about the maximum number of elements used by the method on the data stack and the number of local variables and parameters required by the method. If the combined size of the stack, arguments and local variables is less than 16, all these elements can be stored in the register bank. For methods which require more data stack/stack frame data, the overflow is maintained in a memory-resident stack frame.

[0124] FIG. 2 shows the modifications required to augment the RISC processor for handling non-branching instructions (where an instruction register 200 holds 4 fields of information per instruction—an op-code field I, and three register address fields A, B, and C). The modifications consist of the following:

[0125] A register map circuit (RM) 201, which is described in detail later.

[0126] A J-mode bit 205 in either the PSW or in a separate auxiliary register. This enables/disables the operation of the RM circuit, in effect turning the augmented ARC+ mode on or off (during the execution of a typical JVM program, the J-mode bit is enabled).

[0127] A 4-bit stack counter (sc) register 206, allocated in the ARC auxiliary register bank, together with a 4-bit adder circuit 207 and a stack counter control circuit 208.

[0128] Three phantom registers allocated from the core register extension set 202. The registers are phantom, because they are used as aliases for other registers and provide additional information for the stack counter control circuit.

[0129] The purpose of the modifications is to allow the ARC processor to enable/disable the augmented instruction set (by setting the J bit in a register). With the J bit enabled, the ARC core register space (registers r0 . . . r63) 202 is partitioned into two groups:

[0130] Register numbers in the range 0 to 15 are mapped dynamically into “physical” registers r0 to r15 on the basis of the current value of the SC (stack counter) register 206. The mapping is simply the sum (modulo 15) of the register number and the value of SC 206.

[0131] Register numbers in the range 16 to 63 are mapped directly into the corresponding registers r16 to r63 (except for the phantom registers described below).

[0132] It will be apparent that the register mapping mechanism allows the first 16 registers of the ARC core to be treated as a “rotating” register file. In order to make this into a stack, some means of automatically incrementing and decrementing the SC register 206 has to be provided. In order to accomplish this, use is made of the extended core register range of the ARC processor (registers r32 through r63). Three phantom register numbers are assigned, called from now r0+, r1− and r1—. The register mapping circuit detects the phantom register numbers, and:

[0133] Substitutes the phantom register number with r0 or r1 depending on the exact phantom register (r0 for r0+ and r1 for r1− and r1—).

[0134] Generates an appropriate control signal for use by the stack counter control circuit (increment sc by 1 for r0+, decrement sc by 1 for r1− and decrement sc by 2 for r1—).

[0135] When an instruction does not contain a phantom register number, the value of the SC register 206 is not modified.

[0136] The register mapping mechanism outlined above, allows all the common JVM instructions to be mapped directly into a single ARC+ machine instruction.

[0137] A more detailed implementation of the register mapping mechanism is shown in FIG. 3. The function of two circuits (labeled E and SCC) in the diagram can be clarified as follows. The function of circuit E 303 is to perform the actual register mapping (by generating a mux select value). Circuit E takes two inputs:

[0138] The 6 bit “original” register number.

[0139] The J bit from the status register

[0140] The E circuit generates three control signals:

[0141] The adder mux select signal (to map r0+, r1− and r1—into r0 and r1).

[0142] A control signal into the stack counter controller to determine the value, by which sc is to be modified at the end of the cycle.

[0143] A select signal into the main mux, to determine whether the output is the same as the input (no mapping), or the mapped value.

[0144] The SCC (stack counter controller) 306 takes the stack control outputs of the three E circuits 303 and generates a constant to be added to the SC register 309 at the end of the cycle. This constant can be 0, 1, −1 or −2. It may be assumed that in a “correct” instruction, only one of the three possible operands (A, B or C) can be a phantom register number. In case of conflict, the output of the SCC 306 may be arbitrary.

[0145] FIG. 4 illustrates the modification required to the RISC processor to deal with branching instructions (where the SCC, SC, and auxilliary register holding the J bit are the same as illustrated in FIGS. 2 and 3). It will be appreciated that some decision mechanism will be provided to route non-branching instructions to the circuitry of FIG. 2, and branching instructions to the circuitry of FIG. 4. Referring to FIG. 4, the branching instruction is loaded into the instruction register, and comprises the five Q bits as described above. The fifth Q bit (Q4) is passed to a control circuit C which also receives at an input the J bit and the instruction op-code. Assuming that the J bit is set to turn the stack-based mode on, and the op-code identifies a branching instruction, the control circuit C detects that the bit Q5 is set. The control circuit issues an instruction to the stack counter controller (SCC) to decrement the stack counter SC by 1 at the end of the cycle. The control circuit C then resets bit Q5 to 0 and passes this to the RISC processor core. Bits Q0 to Q5, and the op-code are passed unchanged to the processor core.

[0146] FIG. 5 is a flow diagram illustrating the method of executing a stack-based program described above.

[0147] The invention has been described with reference to a preferred embodiment. Alternatives will be apparent to persons skilled in the art. In particular, an operation different from sum (modulo the bit width of the operand field) may be utilised to perform a different mapping of the operand register number to the mapped register number. Also, different constant values from 0 and 1 may be substituted for the phantom register numbers.

[0148] The key improvement of the approach to executing stack-based instruction sets on a RISC architecture proposed here over traditional coprocessor solutions is due to:

[0149] a) The fact that support for stack-oriented instructions does not require the addition of any additional pipeline stages to the RISC processor and their execution does not involve a mode switch operation and that the underlying RISC instruction set is available in addition to the augmented set in the same operating mode of the processor. The RISC instructions can be utilised to make the stack-based program much more efficient using a combination of the two translation modules (implemented either in hardware or software) described above.

[0150] b) Because no extra pipeline stages need to be added to the RISC processor, the processor's memory system, caches and pipelines do not need to be changed to support efficient execution of stack-based programs. This makes the cost of supporting stack-based execution much smaller in terms of gate-count and complexity, than a coprocessor solution.

[0151] In a modification to the embodiment of FIG. 3, the single stack counter register 309 is replaced with a pair of registers. A first of the registers maintains a pointer to the bottom element of the stack, whilst the second register which contains the number of elements currently held in the stack. The stack counter controller 306 maintains the correct values in the registers. The current stack pointer (i.e. the pointer to the top of the stack) is obtained by summing the contents of the two registers. This modification not only provides the stack pointer, but also facilitates an efficient means for removing elements from and adding elements to the bottom of the stack. Such operations are common when nested function calls are executed, and parts of the stack need to be saved to and restored from external memory.

Claims

1. A method of executing a stack-based program containing branch instructions using a processor having a register-based architecture, the processor having means for implementing a stack using registers of the processor such that the processor may operate in a stack-based mode as well as a register-based mode, the method comprising the steps of:

translating each branch instruction of the stack-based program into a branch instruction of a register-based program and including in the translated instruction an indication that the instruction relates to the stack-based operation mode;

examining each translated branch instruction and, if the instruction includes said indication, updating a stack counter of said means for implementing a stack; and

executing the branch instruction.

2. A method according to claim 1, wherein each register-based branch instruction contains a set of condition flags which define the condition on which branching is to occur.

3. A method according to claim 2, wherein said indication that an instruction relates to the stack-based operation mode is contained in the condition flags.

4. A method according to claim 3, wherein said indication is contained in one of the condition flags.

5. A method according to any one of the preceding claims and comprising translating stack-based instructions, including branching instructions, fetched from the program memory prior to execution of the program and storing the program in memory.

6. A method according to any one of claims 1 to 4, wherein the translation of stack-based instructions fetched from the program memory is carried out on-the-fly.

7. A method according to any one of the preceding claims, wherein the stack based-program is a JVM program, and the processor having a register-based architecture is a RISC processor such that the register-based instructions are RISC instructions.

8. A register-based processor system comprising:

a processor core having a plurality of registers and a stack counter arranged to facilitate access to a stack formed using said registers, the processor core being arranged to execute register-based instructions;

a translation mechanism arranged to fetch stack-based instructions and to translate the fetched instructions into register-based instructions, the translation mechanism comprising means for recognising a branch instruction in the fetched instructions and to include in the corresponding translated instruction an indication that the instruction relates to a stack-based mode of operation; and

means for identifying translated instructions containing said indication and for updating said stack counter in response.

9. A processor according to claim 8, wherein said translation mechanism comprises a set of software instructions which are executed by the processor core.

10. A processor according to claim 8, wherein the translation mechanism comprises circuitry coupled to an input of the processor core or a combination of circuitry coupled to an input of the processor core and a set of software instructions which are executed by the processor core.

11. A processor according to any one of claims 1 to 10, wherein the translation mechanism is arranged to set a flag bit of a translated branch instruction to provide said indication that the instruction relates to a stack-based mode of operation.

12. A processor according to any one of claims 1 to 11, wherein said means for identifying translated instructions containing said indication comprises a circuit coupled to the input of the processor core which tests a flag bit of a translated branch instruction to determine if that instruction is to be executed using the stack-based mode, and if the flag bit indicates that the instruction is to be executed using the stack-based mode, to update the stack counter, and reset the flag bit before passing the instruction to the processor core for execution.

13. A processor according to claim 12, wherein said circuit receives as an additional input a flag bit which can have one of two values, and if the flag bit is set to a first value, the circuit is arranged to is switch the stack-based mode on and if the flag bit is set to the second value, to switch stack-based mode off.

14. A processor according to any one of claims 8 to 13, wherein said stack counter comprises a single register maintaining the counter.

15. A processor according to any one of claims 8 to 13, wherein said stack counter comprises a pair of registers, a first of which maintains a pointer to the bottom of the stack and a second of which contains the size of the stack, and means for adding together the contents of the two registers to obtain a pointer to the top of the stack.