Decoding Instruction To Accommodate Plural Instruction Interpretations (e.g., Different Dialects, Languages, Emulation, Etc.) Patents (Class 712/209)
  • Patent number: 10929132
    Abstract: Disclosed embodiments relate to systems and methods for performing instructions to access a compressed graphic list. In one example, a processor includes fetch and decode circuitry to fetch and decode the single instruction to access the compressed graphic list, and execution circuitry to execute the decoded single instruction to cause access to the compressed graphic list by: receiving, from a load store queue, at a first op-engine associated with a first data location, an indirection request, computing, via the first op-engine, a second data location associated with a second op-engine, computing, via the second op-engine, a third data location associated with a third op-engine responsive to the indirection request, and providing, via the third op-engine, a data response to the load store queue responsive to receiving data from the third data location.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Robert Pawlowski, Scott Hagan Schmittel, Joshua Fryman, Wim Heirman, Jason Howard, Ankit More, Shaden Smith, Scott Cline
  • Patent number: 10789072
    Abstract: A parallel processor comprising elementary processors disposed according to a topology with a predetermined position within this topology and capable of simultaneously executing the same instruction on different data, the instruction relating to at least one operand and/or providing at least one result The instruction comprises, for each operand and/or each result, information relating to the position of a field of action within a table data structure of dimension N type, and the parallel processor calculates the address of each operand and calculates the address of each result within each elementary processor, as a function of the position of the field of action and of the position of the elementary processor within the topology.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: September 29, 2020
    Assignee: THALES
    Inventor: GĂ©rard Gaillat
  • Patent number: 10776114
    Abstract: A method and apparatus provide means for compressing instruction code size. An Instruction Set Architecture (ISA) encodes instructions compact, usual or extended bit lengths. Commonly used instructions are encoded having both compact and usual bit lengths, with compact or usual bit length instructions chosen based on power, performance or code size requirements. Instructions of the ISA can be used in both privileged and non-privileged operating modes of a microprocessor. The instruction encodings can be used interchangeably in software applications. Instructions from the ISA may be executed on any programmable device enabled for the ISA, including a single instruction set architecture processor or a multi-instruction set architecture processor.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: September 15, 2020
    Assignee: ARM Finance Overseas Limited
    Inventor: Erik K. Norden
  • Patent number: 10684984
    Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Eliezer Tamir, Ben-Zion Friedman
  • Patent number: 10579125
    Abstract: An integrated circuit of an aspect includes a power control unit having an interface to receive an indication that one or more instructions of a first type are to be performed by a core. The power control unit also has logic to control a maximum clock frequency for the core based on the indication that the instructions of the first type are to be performed by the core.
    Type: Grant
    Filed: February 27, 2016
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Daniel J. Ragland, Pavithra Sampath, Kirk Pfaender, Kahraman D. Akdemir, Ariel Gur
  • Patent number: 10565040
    Abstract: A device includes a non-volatile memory and a low density parity check (LDPC) decoder configured to receive a representation of a codeword from the non-volatile memory. The LDPC decoder includes multiple data processing units (DPUs) and a control circuit coupled to the DPUs. The control circuit is responsive to an error metric associated with the representation of the codeword and is configured to set a message resolution at least partially based on the error metric and to selectively disable one or more components of the LDPC decoder based on the message resolution.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: February 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yuri Ryabinin, Yan Dumchin
  • Patent number: 10528356
    Abstract: An apparatus and method for supporting simultaneous multiple iterations (SMI) and iteration level commits (ILC) in a course grained reconfigurable architecture (CGRA). The apparatus includes: Hardware structures that connect all of multiple processing engines (PEs) to a load-store unit (LSU) configured to keep track of which compiled program code iterations have completed, which ones are in flight and which are yet to begin, and a control unit including hardware structures that are used to maintain synchronization and initiate and terminate loops within the PEs. The PEs, LSU and control unit are configured to commit instructions, and save and restore context at loop iteration boundaries. In doing so, the apparatus tracks and buffers state of in-flight iterations, and detects conditions that prevent an iteration from completing.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chia-yu Chen, Kailash Gopalakrishnan, Jinwook Oh, Lee M. Saltzman, Sunil K. Shukla, Vijayalakshmi Srinivasan
  • Patent number: 10511626
    Abstract: A method and associated circuits protect data stored in a secure data circuit of a telecommunication device equipped with a near-field communication (NFC) router, a microcontroller, and the secure data circuit. In the method, each message received with the NFC router is parsed to retrieve a communication pipe identifier and an instruction code. The communication pipe identifier and the instruction code are compared to corresponding information in a filter table. Instruction codes of particular messages that attempt to modify a communication pipe by reassigning one end of the communication pipe from the port of the NFC router to a different circuit are acted upon. These messages are blocked from reaching the secure data circuit when the instruction code is not authorized in the filter table, and these messages are permitted when the instruction code is authorized in the filter table.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: December 17, 2019
    Assignees: STMicroelectronics (Rousset) SAS, Proton World International N.V.
    Inventors: Thierry Huque, Olivier Van Nieuwenhuyze, Alexandre Charles
  • Patent number: 10504492
    Abstract: An apparatus for generating dynamic trace data of binary code running on one or more execution units of a Graphics Processing Unit (GPU) though binary instrumentation is presented. In embodiments, the apparatus may include an input interface disposed in the GPU to receive instrumented binary code and communication data, and an output interface disposed in the GPU, and coupled to a memory of a computer hosting the GPU. In embodiments, the memory may be further coupled to the input interface and a Central Processing Unit (CPU) of the computer, the memory having a trace buffer and a control buffer, the control buffer including an overflow flag of the trace buffer. In embodiments, the apparatus may further include an execution unit (EU) disposed in the GPU and coupled to the input interface and to the output interface, to conditionally execute the instrumented binary code and generate dynamic trace data when the overflow flag is not set to indicate an overflow condition.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Sunpyo Hong, Konstantin Levit-Gurevich, Michael Berezalsky, Arik Narkis, Noam Itzhaki
  • Patent number: 10481913
    Abstract: A device protects data dependency for memory access. The device includes a memory and a processor. The processor executes memory access instructions including load instructions and store instructions. The processor includes load circuitry to execute the load instructions; and store circuitry to execute the store instructions. Each memory access instruction includes a token index field containing a token index that associates the memory access instruction with a memory location. The processor further includes dispatch circuitry to dispatch instructions to the load circuitry and the store circuitry; and a token registry to record used token indices according to token index fields in the memory access instructions dispatched by the dispatch circuitry.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: November 19, 2019
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Steve Hengchen Hsu, Hsiao-Han Ma, Chia-An Lin, Wei-Lun Hung, Dan MingLun Chuang
  • Patent number: 10477164
    Abstract: A shift register is described. The shift register includes a plurality of cells and register space. The shift register includes circuitry having inputs to receive shifted data and outputs to transmit shifted data, wherein: i) circuitry of cells physically located between first and second logically ordered cells are configured to not perform any logical shift; ii) circuitry of cells coupled to receive shifted data transmitted by an immediately preceding logically ordered cell comprises circuitry for writing into local register space data received at an input assigned an amount of shift specified in a shift command being executed by the shift register, and, iii) circuitry of cells coupled to transmit shifted data to an immediately following logically ordered cell comprises circuitry to transmit data from an output assigned an incremented shift amount from a shift amount of an input that the data was received on.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: November 12, 2019
    Assignee: Google LLC
    Inventor: Jason Rupert Redgrave
  • Patent number: 10452399
    Abstract: Apparatus and methods are disclosed for example computer processors that are based on a hybrid dataflow execution model. In particular embodiments, a processor core in a block-based processor comprises: one or more functional units configured to perform functions using one or more operands; an instruction window comprising buffers configured to store individual instructions for execution by the processor core, the instruction window including one or more operand buffers for an individual instruction configured to store operand values; a control unit configured to execute the instructions in the instruction window and control operation of the one or more functional units; and a broadcast value store comprising a plurality of buffers dedicated to storing broadcast values, each buffer of the broadcast value store being associated with a respective broadcast channel from among a plurality of available broadcast channels.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: October 22, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Patent number: 10423216
    Abstract: A processor includes first and second processing cores configured to support first and second respective subsets of features of its instruction set architecture (ISA) feature set. The first subset is less than all the features of the ISA feature set. The first and second subsets are different but their union is all the features of the ISA feature set. The first core detects a thread, while being executed by the first core rather than by the second core, attempted to employ a feature not in the first subset and, in response, to indicate a switch from the first core to the second core to execute the thread. The unsupported feature may be an unsupported instruction or operating mode. A switch may also be made if the lower performance/power core is being over-utilized or the higher performance/power core is being under-utilized.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: September 24, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Rodney E. Hooker, Terry Parks, G. Glenn Henry
  • Patent number: 10313641
    Abstract: A shift register is described. The shift register includes a plurality of cells and register space. The shift register includes circuitry having inputs to receive shifted data and outputs to transmit shifted data, wherein: i) circuitry of cells physically located between first and second logically ordered cells are configured to not perform any logical shift; ii) circuitry of cells coupled to receive shifted data transmitted by an immediately preceding logically ordered cell comprises circuitry for writing into local register space data received at an input assigned an amount of shift specified in a shift command being executed by the shift register, and, iii) circuitry of cells coupled to transmit shifted data to an immediately following logically ordered cell comprises circuitry to transmit data from an output assigned an incremented shift amount from a shift amount of an input that the data was received on.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 4, 2019
    Assignee: Google LLC
    Inventor: Jason Rupert Redgrave
  • Patent number: 10310984
    Abstract: A storage apparatus includes a first storage device and a second storage device, out of logical-physical translation information which associates a logical page and a physical page in the second storage device with each other. Non-compressed logical-physical translation information in the first storage device is assumed to constitute a first tier, compressed logical-physical translation information in the first storage device is assumed to constitute a second tier, and compressed logical-physical translation information in the second storage device is assumed to constitute a third tier. The storage apparatus includes tier management information for managing which logical page is included in logical-physical translation information of which of the first tier, the second tier, and the third tier.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: June 4, 2019
    Assignee: HITACHI, LTD.
    Inventor: Atsushi Kawamura
  • Patent number: 10218384
    Abstract: A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: February 26, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Eran Sharon, Idan Goldenberg, Ishai Ilani, Idan Alrod, Yuri Ryabinin, Yan Dumchin, Mark Fiterman, Ran Zamir
  • Patent number: 10089254
    Abstract: Methods and apparatus for dynamic instruction set selection for producing an output parameter based on one or more available input parameters are presented. In an example method, a device selects, from different candidate instruction sets that are each configured to produce a same output parameter, an instruction set that requires one or more input parameters that are each available at the device. In addition, in the example method, the device obtains the output parameter by executing the selected instruction set using the input parameters required by that instruction set. In some examples where more than one candidate instruction sets could be selected based on the available input parameters, the device may select the highest-ranking instruction set for execution.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: October 2, 2018
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Ola Angelsmark, Per Persson
  • Patent number: 10051108
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for providing contextual information for a notification. In one aspect, a method includes receiving, from a user device in response to the user device obtaining a notification in response to an occurrence of a trigger event, a query-independent request for contextual information relevant to the notification, identifying multiple search items from content in the notification, determining a relevance score for each of the multiple search items, selecting one or more of the multiple search items based on the relevance scores, and providing, to the user device for each of the selected one or more multiple search items, a respective user interface element for display with the notification, wherein each user interface element includes contextual information regarding the respective search item.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: August 14, 2018
    Assignee: Google LLC
    Inventors: Gokhan H. Bakir, Marcin M. Nowak-Przygodzki
  • Patent number: 10007520
    Abstract: Systems and methods for using alternate computer instruction sets are disclosed. In one embodiment, a method of program execution using an alternate instruction set may include (1) enabling a computer processor to use an alternate instruction set; (2) a first computer program in memory issuing a first instruction for execution by the computer processor; (3) the computer processor determining that the first instruction issued by the first computer program is in the alternate instruction set; (4) the computer processor translating the first instruction issued by the first computer program; and (5) the computer processor executing the translated instruction.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: June 26, 2018
    Assignee: JPMorgan Chase Bank, N.A.
    Inventor: Scott Ross
  • Patent number: 9990204
    Abstract: A processing element comprises a plurality of function units (16) operable to execute respective functions in dependence upon received instructions in parallel with one another. An instruction controller includes a plurality of instruction pipelines (42). Each of the pipelines (42) is associated with a function unit (16) of the processing element, and is operable to deliver instructions to the function unit concerned for execution thereby. Each pipeline also includes a timing controller operable to receive timing information for a received instruction, and to determine an initial location in the pipeline into which the instruction is to be loaded, and an instruction handler operable to receive an instruction for the function unit associated with the instruction pipeline concerned, and to load that instruction into the initial location determined by the timing controller.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: June 5, 2018
    Assignee: BLUWIRELESS TECHNOLOGY LIMITED
    Inventors: Ray McConnell, Ifor Powell
  • Patent number: 9977664
    Abstract: An application process is switched between asymmetric processor cores having no compatibility in instruction set architectures so that the process can be continuously executed. In an information processing device, when a request to switch an execution subject is generated while a first processor core is executing an application program, a switch process code makes the first processor core specify a basic block being executed at present. The switch process code makes the first processor core execute a first execution code until a branch instruction at the end of the specified basic block, and makes a second processor core execute a second execution code from an instruction at the head of a basic block to be executed next to the specified basic block.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: May 22, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Masakatsu Toyama, Masanori Hayashikoshi
  • Patent number: 9971535
    Abstract: A conversion method for reducing power consumption and computing apparatus using the same are introduced. The computing apparatus includes a conversion unit, a data storage unit and an instruction processing unit. The conversion unit receives a first instruction sequence. In a power saving mode, the conversion unit combines a second instruction sequence having the same function as the first instruction sequence with at least one specific instruction to obtain and output a third instruction sequence. The at least one specific instruction does not belong to an instruction set each instruction included in the first instruction sequence belongs to. The data storage unit includes a volatile part and a non-volatile part. The instruction processing unit is coupled to the conversion unit and the data storage unit, processes the third instruction sequence and manages a storage state of the data storage unit according to the at least one specific instruction.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: May 15, 2018
    Assignee: Industrial Technology Research Institute
    Inventor: Mao-Yin Wang
  • Patent number: 9935975
    Abstract: A hardware-implemented method to support three desirable software properties: encapsulation, referential integrity/capabilities, and transactions. These properties in turn may be used to support software correctness, specifically the enforcement of invariants, and computer security, specifically protecting parts of programs from each other within a single process.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: April 3, 2018
    Inventors: Daniel Shawcross Wilkerson, Mark William Winterrowd
  • Patent number: 9928065
    Abstract: A method and apparatus provide means for compressing instruction code size. An Instruction Set Architecture (ISA) encodes instructions compact, usual or extended bit lengths. Commonly used instructions are encoded having both compact and usual bit lengths, with compact or usual bit length instructions chosen based on power, performance or code size requirements. Instructions of the ISA can be used in both privileged and non-privileged operating modes of a microprocessor. The instruction encodings can be used interchangeably in software applications. Instructions from the ISA may be executed on any programmable device enabled for the ISA, including a single instruction set architecture processor or a multi-instruction set architecture processor.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: March 27, 2018
    Assignee: ARM Finance Overseas Limited
    Inventor: Erik K. Norden
  • Patent number: 9921843
    Abstract: Predictive fetching and decoding for selected instructions (e.g., operating system instructions, hypervisor instructions or other such instructions). A determination is made that a selected instruction, such as a system call instruction, an asynchronous interrupt, a return from system call instruction or return from asynchronous interrupt, is to be executed. Based on determining that such an instruction is to be executed, a predicted address is determined for the selected instruction, which is the address to which processing transfers in order to provide the requested services. Then, fetching of instructions beginning at the predicted address prior to execution of the selected instruction is commenced. Further, speculative state relating to a selected instruction, including, for instance, an indication of the privilege level of the selected instruction or instructions executed on behalf of the selected instruction, is predicted and maintained.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: March 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 9898292
    Abstract: Methods, devices and systems are disclosed that interface a host computer to a specialized processor. In an embodiment, an instruction generation unit comprises attribute, decode, and instruction buffer stages. The attribute stage is configured to receive a host-program operation code and a virtual host-program operand from the host computer and to expand the virtual host-program operand into an operand descriptor. The decode stage is configured to receive the first operand descriptor and the host-program operation code, convert the host-program operation code to one or more decoded instructions for execution by the specialized processor, and allocate storage locations for use by the specialized processor. The instruction buffer stage is configured to receive the decoded instruction, place the one or more decoded instructions into one or more instruction queues, and issue decoded instructions from at least one of the one or more instruction queues for execution by the specialized processor.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: February 20, 2018
    Assignee: Mireplica Technology, LLC
    Inventor: William M. Johnson
  • Patent number: 9891921
    Abstract: The RISC data processor is based on the idea that in case that there are many flag-generating instructions, the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. With the data processor, an instruction for generating flags according to operands' data sizes is defined. To an instruction set handled by the RISC data processor, an instruction capable of executing an operation on operand in more than one data size, which performs a process identical to an operation process conducted on the small-size operand on low-order bits of the large-size operand, and generates flags capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation is added. Thus, the reduction in instruction code space of the RISC data processor tight in instruction code space can be achieved.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: February 13, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Fumio Arakawa
  • Patent number: 9875108
    Abstract: A system, processor, and method to record the interleavings of shared memory accesses in the presence of complex multi-operation instructions. An extension to instruction atomicity (IA) is disclosed that makes it possible for software to infer partial information about a multi-operation execution if the hardware has recorded a dependency due to an instruction atomicity violation (IAV). By monitoring the progress of a multi-operation instruction, the need for complex multi-operation emulation is unnecessary.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: January 23, 2018
    Assignee: Intel Corporation
    Inventors: Gilles A. Pokam, Rolf Kassa, Klaus Danne, Tim Kranich, Cristiano L. Pereira, Justin E. Gottschlich, Shiliang Hu
  • Patent number: 9817791
    Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.
    Type: Grant
    Filed: April 4, 2015
    Date of Patent: November 14, 2017
    Assignees: TEXAS INSTRUMENTS INCORPORATED, TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Srinivas Lingam, Seok-Jun Lee, Johann Zipperer, Manish Goel
  • Patent number: 9792121
    Abstract: A microprocessor includes an instruction translation unit that extracts condition information from the IT instruction and fuses the IT instruction with the first IT block instruction. For each instruction of the IT block, the instruction translation unit: determines a respective condition for the IT block instruction using the condition information extracted from the IT instruction and translates the IT block instruction into a microinstruction. The microinstruction includes the respective condition. Execution units conditionally execute the microinstruction based on the respective condition. For each IT block instruction, the instruction translation unit determines a respective state value using the extracted condition information. The state value comprises the lower eight bits of the IT instruction having the lower five bits left-shifted by N-1 bits, where N indicates a position of the IT block instruction in the IT block.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: October 17, 2017
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Terry Parks, G. Glenn Henry
  • Patent number: 9760379
    Abstract: Embodiments relate to register comparison for register comparison for operand store compare (OSC) prediction. An aspect includes, for each instruction in an instruction group of a processor pipeline: determining a base register value of the instruction; determining an index register value of the instruction; and determining a displacement of the instruction. Another aspect includes comparing the base register value, index register value, and displacement of each instruction in the instruction group to the base register value, index register value, and displacement of all other instructions in the instruction group. Another aspect includes based on the comparison, determining that a load instruction of the instruction group has a probable OSC conflict with a store instruction of the instruction group. Yet another aspect includes delaying the load instruction based on the determined probable OSC conflict.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Hutton, Wen Li, Eric Schwarz
  • Patent number: 9753787
    Abstract: Apparatuses, methods and storage media associated with multiple processor modes execution are described herein. In embodiments, an apparatus may include a processor with a plurality of processor modes, including a first processor mode to address a first address space, and a second processor mode to address a second address space, the second address space including the first address space. The apparatus may further include a signal handler to handle a signal from a kernel, in the first processor mode; and a signal handler wrapper to switch the processor to the second processor mode on delivery of the signal from the kernel, save a current extra context of the second processor mode from the second register file to a user stack, switch the processor back to the first processor mode, then invoke the signal handler to handle the signal. Other embodiments may be described or claimed.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Yihua Jin, Xiao Dong Lin, Yong Wu, Jianhui Li, Xueliang Zhong
  • Patent number: 9753724
    Abstract: A data processing apparatus, method and computer program that perform an operation on one data element such as a register and conditionally select either that register or a further register on which no operation has been performed. The apparatus includes an instruction decoder configured to decode at least one conditional select instruction specifying a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. Data processing operations are controlled by the instruction decoder and the data processor is responsive to the decoded at least one conditional select instruction where the condition does not have the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 5, 2017
    Assignee: ARM Limited
    Inventors: Simon John Craske, Richard Roy Grisenthwaite, Nigel John Stephens
  • Patent number: 9727340
    Abstract: The present invention provides a method and apparatus for scheduling based on tags of different types. Some embodiments of the method include broadcasting a first tag to entries in a queue of a scheduler. The first tag is broadcast in response to a first instruction associated with a first entry in the queue being picked for execution. The first tag includes information identifying the first entry and information indicating a type of the first tag. Some embodiments of the method also include marking at least one second entry in the queue is ready to be picked for execution in response to at least one second tag associated with at least one second entry in the queue matching the first tag.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: August 8, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Achenbach, Teik Tan, Gregory W. Smaus, Ganesh Venkataramanan, Emil Talpes
  • Patent number: 9710674
    Abstract: A method for executing applications on an untrusted device includes selecting one or more applications as sensitive applications. One or more instruction sequences of the said one or more sensitive applications are modified by an external dongle. The one or more sensitive applications are executed on the untrusted device according to the modified instruction sequences. Whether correct execution of the instructions of the said modified instruction sequences has occurred is checked by the external dongle.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: July 18, 2017
    Assignee: NEC CORPORATION
    Inventors: Ghassan Karame, Joao Girao, Wenting Li
  • Patent number: 9652403
    Abstract: A data storage device includes a storage memory device, a control unit suitable for generating a descriptor, which describes a work for controlling the storage memory device, and storing the descriptor in a working memory, and a memory control unit suitable for generating control signals for the storage memory device by fetching an instruction set from an instruction memory based on the descriptor.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: May 16, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jae Woo Kim, Kwang Hyun Kim
  • Patent number: 9558002
    Abstract: In an aspect, a pipelined execution resource can produce an intermediate result for use in an iterative approximation algorithm in an odd number of clock cycles. The pipelined execution resource executes SIMD requests by staggering commencement of execution of the requests from a SIMD instruction. When executing one or more operations for a SIMD iterative approximation algorithm, and an operation for another SIMD iterative approximation algorithm is ready to begin execution, control logic causes intermediate results completed by the pipelined execution resource to pass through a wait state, before being used in a subsequent computation. This wait state presents two open scheduling cycles in which both parts of the next SIMD instruction can begin execution. Although the wait state increases latency to complete an in-progress algorithm, a total throughput of execution on the pipeline increases.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 31, 2017
    Assignee: Imagination Techologies Limited
    Inventors: Kristie Veith, Leonard Rarick, Manouk Manoukian
  • Patent number: 9535699
    Abstract: A processor includes: a first instruction processing unit that, in a first mode, receives a first input including instructions included in a first instruction set; a second instruction processing unit that, in a second mode, receives the first input, the second instruction processing unit having a simpler configuration than the first instruction processing unit; a third instruction processing unit that, in a third mode, receives a second input including instructions included in a second instruction set, the second instruction set including part of the instructions included in the first instruction set, the third instruction processing unit having a simpler configuration than the first instruction processing unit and the second instruction processing unit; a selection unit that selects, according to a mode, a result of decoding by one of the instruction processing units; and an instruction execution unit that executes an instruction according to the selected result of decoding.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: January 3, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Naoki Ochi
  • Patent number: 9531765
    Abstract: A method and system that is configured for receiving a connection request at a server over a fiber channel network from a client using SCSI, generating a virtual connection to service the connection request by the server, determining a load of each one of a set of virtual connection engines executed by the server, set of virtual connection engines to manage resources of a locality domain, and assigning the virtual connection to a virtual connection engine with a minimum load amongst the set of virtual connection engines.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 27, 2016
    Assignee: EMC Corporation
    Inventor: Joseph C. Pittman
  • Patent number: 9489205
    Abstract: A method and system of the compiler-assisted look-ahead instruction-fetch branch-prediction (CLIB) comprising simple, small, and twice as fast instruction caches are designed for improving both speed and accuracy of instruction fetch and branch prediction by prefetching and fetching a type of instructions for accurate, look-ahead instruction prefetching, fetching and branch prediction and another type of instructions for compatible instruction prefetch and fetch. The invention is also designed for converting each basic block found in the program compiled by compilers in prior arts to a look-ahead instruction and a single or plurality of compatible instructions. The invention is also designed for delivering the look-ahead instructions to branch predictors before fetching the compatible instructions of the look-ahead instructions.
    Type: Grant
    Filed: July 3, 2015
    Date of Patent: November 8, 2016
    Inventor: Yong-Kyu Jung
  • Patent number: 9454374
    Abstract: Emulation of instructions that include non-contiguous specifiers is facilitated. A non-contiguous specifier specifies a resource of an instruction, such as a register, using multiple fields of the instruction. For example, multiple fields of the instruction (e.g., two fields) include bits that together designate a particular register to be used by the instruction. Non-contiguous specifiers of instructions defined in one computer system architecture are transformed to contiguous specifiers usable by instructions defined in another computer system architecture. The instructions defined in the another computer system architecture emulate the instructions defined for the one computer system architecture.
    Type: Grant
    Filed: March 3, 2013
    Date of Patent: September 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 9436474
    Abstract: A disassembler receives instructions and disassembles them into a plurality of separate opcodes. The disassembler creates a table identifying boundaries between each opcode. Each opcode is written to memory in an opcode-by-opcode manner by atomically writing standard blocks of memory. Debug break point opcodes are appended to opcode to create a full block of memory when needed. The block of memory may be thirty-two or sixty-four bits long, for example. Long opcodes may overlap two or more memory blocks. Debug break point opcodes may be appended to a second portion of the long opcode to create a full block of memory. A stream fault interceptor identifies when a requested data page is not available and retrieving the data page.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: September 6, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Kristofer Reierson
  • Patent number: 9389870
    Abstract: In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A 1-hot signal is generated that identifies an oldest ready instruction in the first age array and a 1-hot signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: July 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen
  • Patent number: 9384000
    Abstract: Embodiments of the invention relate to a computer system for storing an internal instruction loop in a loop buffer. The computer system includes a loop buffer and a processor. The computer system is configured to perform a method including fetching instructions from memory to generate an internal instruction to be executed, detecting a beginning of a first instruction loop in the instructions, determining that a first internal instruction loop corresponding to the first instruction loop is not stored in the loop buffer, fetching the first instruction loop, optimizing one or more instructions corresponding to the first instruction loop to generate a first optimized internal instruction loop, and storing the first optimized internal instruction loop in the loop buffer based on the determination that the first internal instruction loop is not stored in the loop buffer.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: July 5, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 9367322
    Abstract: In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A major signal is generated that identifies an oldest ready instruction in the first age array and a subset signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: June 14, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen
  • Patent number: 9336180
    Abstract: A microprocessor includes hardware registers that instantiate the IA-32 Architecture EDX and EAX GPRs and hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs. The microprocessor associates with each of the R8-R15 GPRs a respective unique MSR address. In response to an IA-32 Architecture RDMSR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate the EDX:EAX registers. In response to an IA-32 Architecture WRMSR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor writes into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate the EDX:EAX registers. The microprocessor does so even when operating in non-64-modes.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: May 10, 2016
    Assignee: VIA TECHNOLOGIES, INC.
    Inventor: Mark John Ebersole
  • Patent number: 9317301
    Abstract: A microprocessor includes a plurality of registers that holds an architectural state of the microprocessor and an indicator that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA. The microprocessor also includes a hardware instruction translator that translates x86 ISA instructions and ARM ISA instructions into microinstructions. The hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal. The microprocessor also includes an execution pipeline, coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 19, 2016
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: G. Glenn Henry, Terry Parks, Rodney E. Hooker
  • Patent number: 9262165
    Abstract: A vector processor includes an instruction fetching unit configured to acquire an instruction, a decoding/issuing unit configured to decode the instruction and issuing the instruction, an operation group configured to include a plurality of operation units and a register configured to store the element data column, wherein the plurality of operation units include a first operation unit processes a first type instruction and a second operation unit processes a second type instruction and the first type instruction; and when a plurality of divided instructions, for which the element data of an instruction to be issued has been divided, are processed by the second operation unit, in a case where the second type instruction is not present, the decoding/issuing unit issues the divided instructions, and in a case where the second type instruction is present, the decoding/issuing unit issues the instruction to be issued without performing division.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: February 16, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Hiroshi Hatano, Koichi Suzuki
  • Patent number: 9250937
    Abstract: A system-wide service can simultaneously harden multiple running JITs, for example by hooking into the memory protections of a target operating system and randomizing newly generated code on the fly when marked as executable. Some embodiments preserve the contents of the calling stack, presenting each JIT with the illusion that it is executing its own generated code.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: February 2, 2016
    Assignee: The Regents Of The University Of California
    Inventors: Michael Franz, Andrei Homescu, Stefan Brunthaler, Per Larsen
  • Patent number: 9230016
    Abstract: Methods and computer program product relate to user input auto-completion. The methods and product are executable on a processing device in a computing system environment so as to provide an auto-completion scheme with enhanced capabilities that improve user efficiency when performing a task.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: January 5, 2016
    Assignee: Novell, Inc
    Inventors: Allan W. Neill, Scott Alan Isaacson