Method of manufacturing multi-chip stacking package
The present invention discloses a method of manufacturing a multi-chip stacking package. The characteristic of the invention is that after the alignment of the bumps of at least two chips, welded bumps will be generated in a high temperature welding to form a welded bump. Furthermore, one of the at least two chips may only provide bonding pad similar to the Under Bump Metallurgy and may not provide bumps, and using the bonding pad to be welded with the bump on another chip.
1. Field of the Invention
The invention relates to a method of manufacturing a multi-chip stacking package, especially to a method of manufacturing multi-chip package using flip-chip bonding to complete the chip stacking.
2. Background of the Invention
Toward the increasing requirements for portability of electronic consumer products, undoubtedly the multi-chip module packaging technology is the best way to meet such requirements. However, the technologies for integrating the functions of many chips and reducing the area occupied by the package mostly need to stack the chips into a packaging device of 3-D structure.
The first object of the invention is to provide a method for manufacturing a multi-chip stacking package so as to improve the production yield and production steps.
The second object of the invention is to provide a method of manufacturing a multi-chip stacking package with a low profile.
In order to achieve above-mentioned objects, the invention discloses a method of manufacturing multi-chip stacking package. The multi-chip stacking package uses at least two chips, which are bonded together and stacked by flip-chip technique, wherein the chip underneath is attached to/onto a substrate with glue. Each of the at least two chips has an active surface, and the active surface provides a plurality of bonding pads, in which the bonding pad is configured with Under Bump Metallurgy (UBM) and bumps based on the levels. The active surface of the chip underneath further provides a plurality of wire bonding pads on its periphery, and connects the wire bonding pads to the bonding pad of the substrate via the metal bonding wires. The whole package uses an encapsulant to protect the internal circuit and a plurality of solder balls are formed under the substrate so as to electrically connect to the circuit board. The characteristic of the invention is that after the alignment of the bumps of at least two chips, welded bumps will be generated in a high temperature welding to form a welded bump. Furthermore, one of the at least two chips may only provide a bonding pad similar to the Under Bump Metallurgy 43 and may not provide with bumps, and using the bonding pad to be welded with the bump on another chip.
BRIEF DESCRIPTION OF THE DRAWINGSThe invention will be described according to the appended drawings, in which:
All the described embodiments use the package of two chips, but it is also possible to replace the second chip 32 with a stack of the above two chips, which depends on the specification requirement and the functions of the chip to change the package design.
The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those persons skilled in the art without departing from the scope of the following claims.
Claims
1. A method of manufacturing multi-chip stacking package, comprising the steps of:
- forming under bump metallurgies and bumps on a plurality of bonding pads of a first chip and a second chip;
- aligning and contacting said bumps of said first chip with corresponding bumps of said second chip; and
- combining said bumps of said first chip with said bumps of said second chip to form welded bumps.
2. The method of manufacturing multi-chip stacking package of claim 1, wherein the material of said bumps is selected from a group essentially consisting of tin, lead, gold, conductive polymer and the alloy thereof.
3. The method of manufacturing multi-chip stacking package of claim 1, further comprising the steps of:
- forming under bump metallurgies and bumps on a plurality of bonding pads of a third chip, which is parallel to said second chip;
- aligning and contacting said bumps of said first chip with corresponding bumps of said third chip; and
- combining said bumps of said first chip with said bumps of said third chip to form welded bumps.
4. The method of manufacturing multi-chip stacking package of claim 1, further comprising the step of filling underfill inside the space enclosed by neighboring welded bumps.
5. A method of manufacturing multi-chip stacking package, comprising the steps of:
- forming under bump metallurgies on a plurality of bonding pads of a first chip, and forming under bump metallurgies and bumps on a plurality of bonding pads of a second chip;
- aligning and contacting said under bump metallurgies of said first chip with corresponding bumps of said second chip; and
- combining said under bump metallurgies of said first chip with said bumps of said second chip.
6. The method of manufacturing multi-chip stacking package of claim 5, wherein the material of said bumps is selected from a group essentially consisting of tin, lead, gold, conductive polymer and the alloy thereof.
7. The method of manufacturing multi-chip stacking package of claim 5, further comprising the step of filling underfill inside the space enclosed by neighboring welded bumps.
8. The method of manufacturing multi-chip stacking package of claim 5, further comprising the steps of:
- forming under bump metallurgies and bumps on a plurality of bonding pads of a third chip, which is parallel to said second chip;
- aligning and contacting said bumps of said first chip with corresponding bumps of said third chip; and
- combining said bumps of said first chip with said bumps of said third chip by applying a heat and pressure.
Type: Application
Filed: Jun 2, 2004
Publication Date: Jan 6, 2005
Inventor: Jen-Kuang Fang (Kaoshiung)
Application Number: 10/859,279