Molded ball grid array
A BGA and a system implementing a BGA. Specifically, a BGA package is encapsulated after the balls are attached to the package. The backside of the package having the balls disposed thereon may be completely covered by the encapsulant. The encapsulant is disposed in direct contact about a portion of the balls. A liner is provided to facilitate the formation of an unencapsulated portion of each ball. The unencapsulated portion may be used to couple the package to a system.
The present application is a Divisional Application of pending application Ser. No. 10/230,569 filed on Aug. 29, 2002, which is a Continuation-in-part of application Ser. No. 10/120,814 filed on Apr. 11, 2002, which is a continuing application under 37 C.F.R. § 1.53(b) of application Ser. No. 09/568,676 filed on May 11, 2000, which issued as U.S. Pat. No. 6,400,574 on Jun. 4, 2002.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates generally to microelectronic packaging and, more particularly, to a method and apparatus for encapsulating a ball grid array (BGA) in a molding compound.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
The packaging of electrical circuits is a key element in the technological development of any device containing electrical components. Several technologies have been developed to provide a means of mounting these electrical components on a surface of a substrate, such as a printed circuit board (PCB). Fine pitch surface mount (FPT), pin grid array (PGA), and ball grid array (BGA) are examples of leading surface mount technologies.
BGA technology offers several advantages over FPT and PGA. Among the most often cited advantages of BGA are: reduced co-planarity problems, since there are no leads; reduced placement problems; reduced paste printing problems; reduced handling damage; smaller size; better electrical and thermal performance; better package yield; better board assembly yield; higher interconnect density; multi-layer interconnect options; higher number of IO's for a given footprint; easier extension to multi-chip modules; and faster design-to-production cycle time.
A BGA semiconductor package generally includes a semiconductor chip mounted on the top surface of a substrate. The semiconductor chip may be electrically coupled to the substrate by bond wires. The substrate contains conductive routing which allows the signals to pass from the semiconductor chip on the top side of the substrate, through the substrate, and to pads on the backside of the substrate. A plurality of solder balls are deposited and electrically coupled to the pads on the backside of the substrate to be used as input/output terminals for electrically connecting the substrate to a PCB or other external device.
One problem with conventional BGA packaging is the need to protect the electrical interface between the chip and the substrate. To protect the semiconductor chip and bond wires from external elements such as moisture, dust, or impact, the semiconductor chip is often encapsulated in a molding compound. The implementation of the encapsulation process presents many challenges.
BRIEF DESCRIPTION OF THE DRAWINGSAdvantages and features of the invention may become apparent upon reading the following detailed description and upon reference to the drawings in which:
One or more specific embodiments of the present invention will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
Turning now to the drawings, and referring initially to
The device 10 typically includes a power supply 14. For instance, if the device 10 is portable, the power supply 14 would advantageously include permanent batteries, replaceable batteries, and/or rechargeable batteries. The power supply 14 may also include an AC adapter, so the device may be plugged into a wall outlet, for instance. In fact, the power supply 14 may also include a DC adapter, so that the device can be plugged into a vehicle cigarette lighter, for instance.
Various other devices may be coupled to the processor 12 depending upon the functions that the device 10 performs. For instance, a user interface 16 may be coupled to the processor 12. The user interface 16 may include buttons, switches, a keyboard, a light pen, a mouse, and/or a voice recognition system, for instance. A display 18 may also be coupled to the processor 12. The display 18 may include an LCD display, a CRT, LEDs, and/or an audio display, for example. Furthermore, an RF subsystem/baseband processor 20 may also be coupled to the processor 12. The RF subsystem/baseband processor 20 may include an antenna that is coupled to an RF receiver and to an RF transmitter (not shown). A communications port 22 may also be coupled to the processor 12. The communications port may be adapted to be coupled to a peripheral device 24, such as a modem, a printer, or a computer, for instance, or to a network, such as a local area network or the Internet, for instance. Volatile memory 26 and non-volatile memory 28 may also be coupled to the processor 12.
Alternately, a board-on-chip (BOC) circuit package may be encapsulated, with molding compound disposed on both surfaces of the substrate 51, as illustrated in
As previously described,
In the present exemplary embodiment, the protruding portion of the solder ball 70 may have a height H of about 0.15 mm with respect to the surface of the encapsulant 164. As can be appreciated, the diameter of the solder balls 70 and the height of the protrusion may vary, depending on the specific application. Further, the amount of the solder balls 70 that is encapsulated may be also vary. For instance, the encapsulant 164 may be disposed to cover an amount of the surface area of the solder ball 70 defined by about 40% to about 85% of the diameter D of the solder ball 70 and more typically, about 50% to about 70%. According to the present dimensions, a surface area defined by approximately 62% of the diameter of the solder ball 70 is encapsulated in the present exemplary embodiment.
While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.
Claims
1. A molded ball grid array comprising:
- a substrate having a first surface and a second surface;
- a plurality of conductive balls coupled to the first surface of the substrate;
- a semiconductor device coupled to the second surface of the substrate; and
- an encapsulant disposed over the first surface of the substrate and disposed conformally about the conductive balls, wherein the encapsulant conforms to the shape of the plurality of conductive balls and covers only a portion of the surface area of the plurality of conductive balls.
2. The molded ball grid array, as set forth in claim 1, wherein the semiconductor device comprises a memory device.
3. The molded ball grid array, as set forth in claim 1, wherein the semiconductor device is electrically coupled to the substrate.
4. The molded ball grid array, as set forth in claim 1, wherein the encapsulant is disposed on at least a portion of the semiconductor device.
5. The molded ball grid array, as set forth in claim 1, wherein the plurality of conductive balls comprises a plurality of solder balls.
6. The molded ball grid array, as set forth in claim 1, wherein the encapsulant comprises a molding compound.
7. The molded ball grid array, as set forth in claim 1, wherein the encapsulant comprises a resin.
8. The molded ball grid array, as set forth in claim 1, wherein the encapsulant is disposed conformally around the conductive balls and covers a portion of the conductive balls, wherein the portion is a surface area defined by about 40% to about 85% of the diameter of the conductive balls.
9. The molded ball grid array, as set forth in claim 1, wherein the encapsulant is disposed conformally around the conductive balls and covers a portion of the conductive balls, wherein the portion is a surface area defined by about 50% to about 70% of the diameter of the conductive balls.
10. The molded ball grid array, as set forth in claim 1, wherein the encapsulant is disposed conformally around the conductive balls and covers a portion of the conductive balls, wherein the portion is a surface area defined by greater than 50% of the diameter of the conductive balls.
11. A system comprising:
- a processor; and
- a package operatively coupled to the processor, wherein the package comprises: a substrate having a first surface and a second surface; a plurality of conductive balls coupled to the first surface of the substrate; a semiconductor device coupled to the second surface of the substrate; and an encapsulant disposed over the first surface of the substrate and disposed conformally about the conductive balls, wherein the encapsulant conforms to the shape of the plurality of conductive balls and covers a portion of the surface area of the plurality of conductive balls.
12. The system, as set forth in claim 11, wherein the semiconductor device comprises a memory device.
13. The system, as set forth in claim 11, wherein the semiconductor device is electrically coupled to the substrate.
14. The system, as set forth in claim 11, wherein the encapsulant is disposed on at least a portion of the semiconductor device.
15. The system, as set forth in claim 11, wherein the plurality of conductive balls comprises a plurality of solder balls.
16. The system, as set forth in claim 11, wherein the encapsulant comprises a molding compound.
17. The system, as set forth in claim 11, wherein the encapsulant comprises a resin.
18. The system, as set forth in claim 11, wherein the encapsulant is disposed conformally around the conductive balls and covers a portion of the conductive balls, wherein the portion is a surface area defined by about 40% to about 85% of the diameter of the conductive balls.
19. The system, as set forth in claim 11, wherein the encapsulant is disposed conformally around the conductive balls and covers a portion of the conductive balls, wherein the portion is a surface area defined by about 50% to about 70% of the diameter of the conductive balls.
20. The system, as set forth in claim 11, wherein the encapsulant is disposed conformally around the conductive balls and covers a portion of the conductive balls, wherein the portion is a surface area defined by greater than 50% of the diameter of the conductive balls.
Type: Application
Filed: Aug 31, 2004
Publication Date: Feb 10, 2005
Inventors: William Stephenson (Nampa, ID), Bret Street (Meridian, ID), Todd Bolken (Meridian, ID)
Application Number: 10/930,520