Semiconductor device and a method of manufacturing the same
A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p−type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p−type semiconductor region is formed under a n+type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.
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The present application claims priority from Japanese Patent application JP 2003-286142 filed on Aug. 4, 2003, the content of which is hereby incorporated by reference as if set forth in the entirety herein.
FIELD OF THE INVENTIONThe invention relates to a semiconductor device and for a method of manufacturing the same, and in particular, to a semiconductor device and method employing power MISFETs (Metal Insulator Semiconductor Field Effect Transistors).
BACKGROUND OF THE INVENTIONIn the case of a trench (groove) gate type power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed in a structure incorporating, for example, a p-type epitaxial layer as an upper layer of an n+type substrate, it is known to reduce the risk of punch-through breakdown of the trench gate by forming an n-type drain region extended between the n+type substrate and the bottom of a trench, and by forming a junction of the n-type drain region and the p-type epitaxial layer extended between the ntype substrate and a partition wall of the trench. This is illustrated in, for example, Japanese Patent Laid-Open No. 2000-164869.
It is also known to improve switching loss of the trench gate power MOSFET by providing an n−type epitaxial layer doped to have a first conductivity type, and a well layer doped to have a second conductivity type, over a semiconductor substrate heavily doped to have the first conductivity type, thereby providing a deep trench gate, isolated by an insulating layer, inside an upper side layer made up of the n−type epitaxial layer and the well layer, and thereby providing a drain region of high conductivity under the trench gate. It is further known to provide source regions heavily doped to have the first conductivity type, adjacent to the trench gate, and to provide a main body region doped more heavily than the well layer, in the upper part of the well layer, to thereby reduce ON-resistance of the drain region. This is illustrated, for example, in Japanese Patent Laid-Open No. 2000-299464.
A power transistor, such as the power MOSFET, may be used for high power applications, such as wherein the power is not less than several watts. One such power transistor, a power MISFET, may be a vertical type and/or a lateral type MISFET, depending on the structure of the gate thereof. A MISFET may be further classified as a trench (groove) gate type, or a planar gate type.
A power MISFET may be used as a switching element of a DC-DC converter, for example, such as for use as a power source circuit for a computer. Since there has recently been a trend of larger current requirements for a CPU (Central Processing Unit) of a computer, to which the DC-DC converter supplies power, a larger current is required of the DC-DC converter as well. Requiring larger currents may cause an increase in ON-loss for a power MISFET. Accordingly, lower ON-resistance also is requited of a power MISFET used in a DC-DC converter.
In a trench gate type power MISFET, a deep groove is formed in a top, element-forming surface of a semiconductor substrate (hereinafter referred to as a substrate), and a gate is formed by embedding a conductor in the groove. Further, in a planar gate type power MISFET, a gate is formed over a top surface of a substrate through the intermediary of a gate insulator. Accordingly, in the trench gate type power MISFET, a current flow path in the substrate becomes shorter as compared with a planar gate type power MISFET, so that ON-resistance can be reduced. However, since a gate insulator is formed on the sidewalls and bottom surface of the groove, there may be an increase in capacitance due to the gate insulator acting as a capacitance insulator, and the gate part acting as a capacitance electrode, as the groove is rendered deeper. On the other hand, in a planar gate type power MISFET, capacitance from the gate insulator acting as the capacitance insulator and the gate acting as the capacitance electrode is reduced as compared with the trench gate type power MISFET, but the number of the gate parts that can be disposed per unit area is reduced if a sufficient gate length to prevent pinch off is present. Hence, if an area of a semiconductor chip, over which the planar gate type power MISFET is formed is constant, the number of the gate parts that can be disposed on the semiconductor chip is less than that in the case of a trench gate type power MISFET. As a result, in the case of the planar gate type power MISFET, ON-resistance of the semiconductor chip increases as compared with the trench gate type power MISFET. Hence, if the trend for the DC-DC converter to higher frequency and larger current continues, the known art cannot simultaneously meet lower ON-resistance and lower capacitance required of a power MISFET.
Thus, the need exists for a semiconductor device and method that provides a power MISFET that simultaneously provides lower ON-resistance and lower capacitance.
SUMMARY OF THE INVENTIONA power MISFET, may include a multitude, such as, for example, several tens of thousands, of finely patterned MISFETs may be connected in parallel. Such a power MISFET may be used as a switching element of a DC-DC converter, for example, such as for use as a power source circuit for a computer, such as a desktop type, note type, server, and the like. Minimization of capacitance for a choke coil, I/O, and so forth, as well as fast response to variation in load, is required of a DC-DC converter. Accordingly, there is a trend for a DC-DC converter towards higher frequency, and as the DC-DC converter operates higher in frequency, an increase in switching loss and drive loss may occur in a power MISFET. Since the switching loss is proportional to a feedback capacitance of a power MISFET, and the drive loss is proportional to an input capacitance, reduction in these capacitances is required for a power MISFET used in a DC-DC converter.
The trench gate type power MISFET shown in
However, because the groove 103 having the gate 105 formed therein is at a depth as deep as, for example, about 1 μm, the gate insulator may act as a capacitance insulator and the gate may act as a capacitance electrode. Input capacitance among the capacitance components is proportional to a length of the periphery of the groove 103 (a surface area of the groove 103 under the n+type semiconductor region 111), and feedback capacitance is proportional to a distance D 12 of a portion of the groove 103 extending from the p−type semiconductor region 109 toward the n−type single crystal silicon layer 102 (a surface area of the potion of the groove 103, in contact with the n−type single crystal silicon layer 102). Accordingly, narrowing a width of the groove 103 reduces the input capacitance, and reducing the distance D12 of the portion of the groove 103 extending from the p−type semiconductor region 109 toward the n−type single crystal silicon layer 102 (thus rendering the groove shallower) reduces feedback capacitance.
Nonetheless, there are limits to process dimensions for narrowing the width of the groove 103, and if the groove 103 is rendered too narrow, an increase in resistance of the gate 105 results. Furthermore, to render the groove 13 shallower, a junction is needed between the p−type semiconductor region 109 and the n−type single crystal silicon layer 102 at a position correspondingly shallower (shallower junctioning). In the case of such shallower junctioning, when a voltage is applied between the drain and the source, depletion may occurs to the channel layer (the p−type semiconductor region 109), thereby causing punch through for the known art does not allow for the reduction of capacitance by rendering the groove shallower while preventing.
If the impurity concentration of the p−type semiconductor region 109 is raised to prevent depletion from occurring to the channel layer, the threshold voltage of the MISFET may increase, resulting in an increase in ON-resistance. Further, if the p−type semiconductor region 109 has the same depth as that of the groove 103 in order to reduce the distance of the groove 103, the bottom of the groove 103 may be covered by the p−type semiconductor region 109 due to manufacturing variation of the groove 103, and the threshold voltage of the MISFET thus increases, thereby resulting in an increase in the ON-resistance.
The present invention achieves lower ON-resistance and lower capacitance for trench gate type power MISFETs. In accordance with an aspect of the invention, there is provided a semiconductor device having MISFETs, including: a first semiconductor layer having a first conductivity type, formed over the top surface of a semiconductor substrate; a second semiconductor layer having a second conductivity type opposite the first conductivity type, formed over the first semiconductor layer; a plurality of first groove parts of not more than 1 μm in depth, formed in the top surface of the semiconductor substrate, wherein at least a portion of respective bottoms of ones of the first groove parts are in contact with the first semiconductor layer; a first insulating film formed on the sidewall and bottom of each of the first groove parts; a first conductor formed over the first insulating film, wherein the first conductor fills up the respective first groove parts; a third semiconductor layer having the first conductivity type, formed in the second semiconductor layer adjacent to respective ones of the first groove parts; a fourth semiconductor layer having the second conductivity type, formed in the second semiconductor layer between adjacent ones of the first groove parts; and a first electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer, wherein the first semiconductor layer and the third semiconductor layer form a source or a drain of each of the MISFETs, the second semiconductor layer forms a channel forming region of each of the MISFETs, and a fifth semiconductor layer having the second conductivity type and higher in impurity concentration than the second semiconductor layer is formed under the third semiconductor layer, in the second semiconductor layer.
The invention provides in an aspect a method of manufacturing a semiconductor device having MISFETs, including the steps of:
-
- (a) forming a first semiconductor layer, having a first conductivity type, over the top surface of a semiconductor substrate;
- (b) introducing a dopant having a second conductivity type opposite the first conductivity type into the semiconductor substrate, and forming a second semiconductor layer having the second conductivity type over the first semiconductor layer;
- (c) forming a plurality of first groove parts in the top surface of the semiconductor substrate;
- (d) forming a first insulating film inside the respective first groove parts;
- (e) embedding a first conductor in the respective first groove parts to thereby form a gate electrode;
- (f) introducing a dopant having the first conductivity type into the semiconductor substrate to thereby form a third semiconductor layer having the first conductivity type adjacent to the respective first groove parts;
- (g) introducing a dopant having the second conductivity type into the semiconductor substrate to thereby form a fifth semiconductor layer having the second conductivity type under the third semiconductor layer and within the second semiconductor layer;
- (h) forming a plurality of second groove parts each penetrating through the third semiconductor layer to be disposed between adjacent ones of the gate electrodes;
- (i) introducing a dopant having the second conductivity type into the semiconductor substrate from the respective bottoms of the second groove parts to thereby form a fourth semiconductor layer having the second conductivity type in the second semiconductor layer to cover the respective bottoms of the second groove parts; and
- (j) filling the second groove parts to thereby form a first electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer,
- wherein the first groove parts are formed to have a depth not more than 1 μm, and wherein at least part of the respective bottoms of the first groove parts are in contact with the first semiconductor layer, and wherein the fifth semiconductor layer is formed to be higher in impurity concentration than the second semiconductor layer, thereby forming MISFETs that each have the first semiconductor layer and the third semiconductor layer as a source or a drain thereof, and the second semiconductor layer as a channel forming region thereof.
Thus, the present invention provides a semiconductor device and method that provides a power MISFET that simultaneously provides lower ON-resistance and lower capacitance.
BRIEF DESCRIPTION OF THE DRAWINGSThe various features of the present invention will now be described in greater detail with reference to the drawings of aspects of the present invention, and various related elements thereof, wherein like reference numerals designate like elements, and wherein:
It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for purposes of clarity, many other elements found in a typical semiconductor device and method. Those of ordinary skill in the art will recognize that other elements are desirable and/or required in order to implement the present invention. But because such elements are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements is not provided herein. The disclosure herein is directed to all such variations and modifications to the applications, networks, systems and methods disclosed herein and as will be known, or apparent, to those skilled in the art.
As shown in
As shown in
Subsequently, as shown in
As shown in
Subsequently, by use of a photo resist film patterned by photolithographic techniques as a mask, the silicon oxide film 3 is etched to thereby remove unnecessary portions thereof. By so doing, a region whereat the silicon oxide film 3 is formed that is underneath the polysilicon film pattern 11 becomes an isolation region, and regions defined by the isolation region become element forming regions (active regions).
As shown in
Subsequently, by use of a photo resist film patterned by photolithographic techniques as a mask, dopant ions (for example B) having the p-type conductivity may be implanted into the n− type single crystal silicon layer 1B at a concentration in the order of 3×1012 ions/cm2, thereby forming a p-type semiconductor region (fifth semiconductor layer) 14 higher in impurity concentration than the p−type semiconductor region 13. The photo mask uses in patterning the photo resist film at this stage may be reused from the a photo mask used in patterning the photo resist film at the time of forming the p−type semiconductor region 13, for example. By so doing, it becomes unnecessary to prepare a new photo mask for use in the formation of the p-type semiconductor region 14, thus enabling a reduction in manufacturing cost of the semiconductor device. Thereafter, by use of a photo resist film patterned by photolithographic techniques as a mask, dopant ions {for example, As (arsenic)} having the n-type conductivity are implanted into the n− type single crystal silicon layer 1B. Subsequently, by applying heat treatment to the substrate 1, the dopant ions are caused to undergo diffusion, thereby forming an n+type semiconductor region (a third semiconductor layer) 15 over the p-type semiconductor region 14 inside the p−type semiconductor region 13. Thus are formed respective power MISFETs having the drain region in the n+type single crystal silicon substrate 1A and the n type single crystal silicon layer 1B, and the source region in the n+type semiconductor region 15. Further, the p-type semiconductor region 14 may serve as a punch-through stopper layer for the respective power MISFETs.
As shown in
As shown in
As shown in FIGS. 9 to 11, after thinly depositing a TiW (titanium-tungsten) film serving as a barrier conductor film in the upper part of the insulating film 16, including the inside of each of the contact grooves 17 as well as the inside of each of the contact grooves 18, by, for example, sputtering, heat treatment is applied to the substrate 1. Subsequently, an Al (aluminum) film (a second conductor) lower in resistivity than the polysilicon film for forming the gate electrodes 10 may be deposited on top of the TiW film by, for example, sputtering. The barrier conductor film, in part, prevents an undesirable reactive layer from being formed due to Al contacting with the substrate (Si). As discussed hereinabove, “the Al film” includes Al as the main constituent, and may contain other metals as will be apparent to those skilled in the art.
Subsequently, by use of a photo resist film patterned by photolithographic techniques as a mask, the TiW film and the Al film may be etched, thereby forming a gate interconnect (second electrode, a first part) 21 electrically connected to the gate electrodes 10, a source pad (a first electrode) 22 electrically connected to the n+type semiconductor region 15 serving as the source region for the respective power MISFETs, a gate pad GP electrically connected to the gate interconnect 21, and interconnects L1, L2, and L3, electrically connected to the source pad 22.
As discussed hereinabove, the grooves 7 may be formed to have a depth D1 as shallow as about 1 μm or less. By rendering the grooves 7 shallower, it is possible to reduce an input capacitance among capacitive components in a gate insulator (thermal oxidation film 9) that cause the gate insulator to act as a capacitance insulator and the gate electrodes 10 to act as capacitance electrodes. In the case of the gate electrodes 10 acting as capacitance electrodes and the gate insulator (thermal oxidation film 9) acting as the capacitance insulator, a gate capacitance can be rendered to be not more than about 1×10−3 pF per 1 μm in a direction in which the gate electrodes 10 (grooves 7) extend in a given plane, if a voltage of 0V is applied to the gate electrodes 10 and the source region (the n+type semiconductor region 15), while a voltage varying from 0V to 10V at a frequency of 1 MHz is applied to the drain region (the n+type single crystal silicon substrate 1A and the n type single crystal silicon layer 1B). For example, if the gate electrodes 10 (grooves 7) are formed in the stripe-like pattern shown in
In conjunction with rendering the grooves 7 shallower, the p−type semiconductor region 13 may be formed at a shallow depth and a junction of the p−type semiconductor region 13 and the n−type single crystal silicon layer 1B may be set at a shallow position (shallower junctioning). In the case of such shallower junctioning, however, when a voltage is applied between the drain and the source, depletion may occur to the channel layer (the p−type semiconductor region 13) for the respective power MISFETs, resulting in punch through. If the impurity concentration of the p−type semiconductor region 13 is raised in order to prevent the depletion from occurring to the channel layer, the threshold voltage of the power MISFET may become higher, resulting in an increase in the ON-resistance. Accordingly, the p-type semiconductor region 14 may be locally higher in impurity concentration than the p type semiconductor region 13, and is formed inside the p−type semiconductor region 13 without raising the impurity concentration of the p−type semiconductor region 13, thereby causing the p-type semiconductor region 14 to function as a punch-through stopper layer. By so doing, the occurrence of punch through can be prevented, as can be a rise in threshold voltage and an increase in the ON-resistance. In other words, reduction of the input capacitance can be implemented while preventing the occurrence of punch through. The threshold voltage can be held to not higher than about 2V.
The sum of a dopant dose for the formation of the p−type semiconductor region 13, and a dopant dose for the formation of the p-type semiconductor region 14, may be rendered similar in magnitude as compared to a dopant dose for the formation of the p−type semiconductor region 13 in the first case of a power MISFET with grooves 7 having a depth of about 1 μm or more, and without a punch-through stopper layer (the p-type semiconductor region 14). As a result, the dopant dose for the formation of the p−type semiconductor region 13 may be reduced as compared with that in the first case power MISFET. Furthermore, as compared with the first case power MISFET, the groove 7 may become shallower in depth, so that in heat treatment after dopant implantation for the formation of the p−type semiconductor region 13, applied in order to form the p−type semiconductor region 13 in such a way as not to cover the bottom of the groove 7, and to implement the shallower junctioning of the p−type semiconductor region 13 and the n−type single crystal silicon layer 1B, a treatment temperature may be lowered. The treatment time may be shortened as compared with that in the manufacturing process for the first case power MISFET. Further, the p-type semiconductor region 14 serving as the punch-through stopper layer is may be formed after the heat treatment for the formation of the p−type semiconductor region 13. By so doing, time for heat treatment applied to the substrate 1 after dopant implantation for the formation of the p-type semiconductor region 14 can be shortened, so that localized formation of the p-type semiconductor region 14 inside the p−type semiconductor region 13 becomes possible. Still further, as for the n+type semiconductor region 15 serving as the source region of the power MISFET, during heat treatment applied after dopant implantation for the formation of the n+type semiconductor region 15, treatment time is may be shortened as much as possible in order to form the same at a shallow depth, and adoption of a short heat treatment time, such as, for example, by a lamp anneal treatment, may occur.
Further, by forming the groove 7 at a shallower depth, manufacturing variation in depth can be reduced, so that a distance D2 of a portion of the groove 7, extending from the p−type semiconductor region 13 toward with the n−type single crystal silicon layer 1B, can be reduced. That is, among the capacitance components in the gate insulator (the thermal oxidation film 9) acting as a capacitance insulator, and the gate electrodes 10 acting as the capacitance electrodes, a feedback capacitance is proportional to the distance of the portion of the groove 7 extending from the p−type semiconductor region 13 toward with the n−type single crystal silicon layer 1B. Accordingly, as a result of reduction in the distance of the portion of the groove 7 extending from the lower edge of the p−type semiconductor region toward with the n−type single crystal silicon layer 1B, the feedback capacitance can be reduced.
With regard to the p−type semiconductor region 13, the region 13 is designed so as to have a depth shallower by, for example, not less than about 10% of the respective depths of the grooves 7, in order to prevent the p−type semiconductor region 13 from covering the bottoms of the grooves 7. However, since the grooves 7 are to have a depth about 1 μm or less, the distance D2 of the portion of the groove 7, extending from the p−type semiconductor region 13 toward the n−type single crystal silicon layer 1B, can be rendered not more than about 0.1 μm.
In addition, as a result of the formation of the p-type semiconductor region 14, it becomes possible to reduce base resistance of a parasitic npn bipolar transistor developed by the n−type single crystal silicon layer 1B acting as a collector, the p−type semiconductor region 13 acting as a base, and the n+type semiconductor region 15 acting as an emitter. Accordingly, avalanche yield strength of the power MISFET can be enhanced.
Experimentation has been performed to examine occurrence of punch through in the p−type semiconductor region 13 serving as the channel layer in the case wherein the p-type semiconductor region 14 serves as the punch-through stopper layer.
The power MISFETs may be used as switching elements (High-side MISFETQH and Low-side MISFETQL) in, for example, a DC-DC converter circuit, as shown in
1/2×(tr+tf)×Id×Vds×f,
and a drive loss can be expressed as:
Qg×Vgs×f.
Based on these formulae, the switching loss and the drive loss are proportional to a frequency, such that the switching loss and the drive loss increase as the circuit operation frequency becomes higher. Further, the switching loss is proportional to the feedback capacitance of the power MISFET, and the drive loss is proportional to the input capacitance of the power MISFET. As previously described, since the feedback capacitance as well as the input capacitance of the power MISFET can be reduced, the loss of the DC-DC converter can be significantly reduced. Thus, it is possible to implement a higher efficiency DC-DC converter system through the use of the present invention.
However, if the grooves 7 (refer to
For this reason, a “gate finger” structure, as shown in
As shown in
The localized formation of the p-type semiconductor region 14 may be implemented in the p−type semiconductor region 13, as discussed hereinthroughout. Because the heat treatment time for the formation of the p-type semiconductor region 14 may be short in duration, a formation position of the p-type semiconductor region 14, and a peak impurity concentration, may be decided by implantation energies for B ions as dopant ions. Accordingly, concentration distribution must be closely monitored, due to channeling of the B ions. Since the B ions are small in atomic radius, there is a particular concern in this regard with respect to the B ions.
Hence, as described with reference to
As shown in
After the formation of the gate pad GP, the gate interconnect 21, and the source pad 22, for example, a polyimide resin film as a protective film may be applied over the substrate 1, and portions of the polyimide resin film, on top of the gate interconnect 21 and the source pad 22, may be removed by exposure and development, thereby forming openings.
Subsequently, after protecting the surface of the substrate 1 with, for example, a tape, the substrate 1 may be turned upside down such that a protected face thereof is on the underside, and the back surface of the n+type single crystal silicon substrate 1A is on the upper side. Subsequently, for example, a Ti (titanium) film, a Ni (nickel) film, and an Au (gold) film, as electrically conductive films, may be sequentially deposited over the back surface of the n+type single crystal silicon substrate 1A by, for example, a sputtering process, thereby forming a stacked film. The stacked film may serve as an extraction electrode (drain electrodes) for the drain (the n+type single crystal silicon substrate 1A and the n−type single crystal silicon layer 1B).
When the protection, such as the tape, is removed, and after forming bump electrodes made of, for example, Au, over the openings formed in the polyimide resin film, dicing may be applied to the substrate, along, for example, dividing regions, thereby dividing the substrate into individual chips. Thereafter, the individual chips may be placed on respective lead frames (mounting boards) having, for example, external pins, and may be encapsulated (mounted) with resin or the like.
As shown in
As described with reference to
The n−type semiconductor region 13A described can be formed by implanting n-type dopant ions (for example, As) from the bottom of the groove 7, after the formation of the groove 7 but prior to the formation of the thermal oxidation film 9, using the silicon oxide film 3 (refer to
As shown in
As shown in
The semiconductor device according to the present invention can be used as a switching element of a DC-DC converter for use as a power source circuit of, for example, a computer.
If not otherwise stated herein, it may be assumed that all components and/or processes described heretofore may, if appropriate, be considered to be interchangeable with similar components and/or processes disclosed elsewhere in the specification. It should be appreciated that the systems and methods of the present invention may be configured and conducted as appropriate for any context at hand. The embodiments described hereinabove are to be considered in all respects only as illustrative and not restrictive. As such, all modifications and variations of the present invention that come within the meaning, range, and equivalency of the claims hereinbelow are to be embraced within the scope thereof.
Claims
1. A semiconductor device including a plurality of MISFETs, comprising:
- a first semiconductor layer having a first conductivity type, formed over a first surface of a semiconductor substrate;
- a second semiconductor layer having a second conductivity type opposite to the said first conductivity type, formed over said first semiconductor layer;
- a plurality of first groove parts equal to or less than 1 μm in depth, formed in said first surface of said semiconductor substrate, wherein at least a portion of said first groove parts are in contact with said first semiconductor layer;
- a first insulating film formed over the sidewall and bottom of each of said first groove parts;
- a first conductor formed over said first insulating film, wherein said first conductor fills at least a portion of each of said first groove parts;
- a third semiconductor layer formed in said second semiconductor layer having said first conductivity type, wherein said third semiconductor layer is adjacent to each of said first groove parts;
- a fourth semiconductor layer having said second conductivity type, formed in the second semiconductor layer between the first groove parts adjacent to each other; and
- a first electrode electrically connected to said third semiconductor layer and said fourth semiconductor layer;
- wherein said first semiconductor layer and said third semiconductor layer form one selected from the group consisting of a source and drain of each of said plurality of MISFETs, and wherein said second semiconductor layer forms a channel forming region of each of said plurality of MISFETs; and
- wherein a fifth semiconductor layer having said second conductivity type and a higher impurity concentration than said second semiconductor layer, is formed in said second semiconductor layer.
2. A semiconductor device according to claim 1, wherein said fifth semiconductor layer forms a punch-through stopper layer.
3. A semiconductor device according to claim 1, further comprising a second electrode electrically connected to said first conductor, formed of a second conductor lower in resistivity than said first conductor.
4. A semiconductor device according to claim 3,
- wherein said plurality of MISFETs are formed in at least one chip region of said semiconductor substrate, and
- wherein said second electrode has a first part formed along the periphery of said at least one chip region and a second part extended in said at least one chip region on at least a portion of the inner side of said first part.
5. A semiconductor device according to claim 1, wherein said first groove parts each have a depth equal to or less than 1.1 times a depth of said second semiconductor layer.
6. A semiconductor device according to claim 5, wherein the magnitude of a portion of each of said first groove parts, extending from said second semiconductor layer, is less than or about 0.1 μm.
7. A semiconductor device according to claim 1 wherein a sixth semiconductor layer having said first conductivity type is formed under said first groove parts.
8. A semiconductor device according to claim 11, wherein the threshold voltage of each of said plurality of MISFETs is less than or about 2V.
9. semiconductor device according to claim 1,
- wherein a second groove part penetrating from said first surface of said semiconductor substrate through said third semiconductor layer is formed between said first groove parts adjacent to each other,
- wherein said fourth semiconductor layer is formed to cover at a portion of said second groove parts, and
- wherein said first electrode is formed to fill at least a portion of said second groove parts.
10. A semiconductor device according to claim 1, wherein each of said plurality of MISFETs is for use as a switching element of a DC-DC converter.
11. A semiconductor device including a plurality of MISFETs, comprising:
- a first semiconductor layer having a first conductivity type, formed over a first surface of a semiconductor substrate;
- a second semiconductor layer having a second conductivity type opposite to said first conductivity type, formed over said first semiconductor layer;
- a plurality of first groove parts having a depth less than or equal to 1 μm, and less than or equal to 1.1 times a depth of said second semiconductor layer, formed in said first surface of said semiconductor substrate, wherein at least a lower portion of the said first groove parts is in contact with said first semiconductor layer;
- a first insulating film formed over at least a portion of a sidewall and bottom of each of said first groove parts;
- a first conductor formed over said first insulating film, filling up at least a portion of said first groove parts;
- a third semiconductor layer having said first conductivity type, formed in said second semiconductor layer adjacent to said first groove parts;
- a fourth semiconductor layer having said second conductivity type, formed in said second semiconductor layer between adjacent ones of said first groove parts;
- a first electrode electrically connected to said third semiconductor layer and said fourth semiconductor layer; and
- a second electrode electrically connected to said first conductor, formed of a second conductor lower in resistivity than said first conductor;
- wherein said first semiconductor layer and said third semiconductor layer form one selected from the group consisting of a source and a drain of each of said plurality of MISFETs, and said second semiconductor layer forms a channel forming region for each of said plurality of MISFETs;
- wherein a fifth semiconductor layer having said second conductivity type and a higher impurity concentration than said second semiconductor layer, is formed in said second semiconductor layer; and
- wherein said second electrode has a first part formed along the periphery of at least one chip region and a second part extended in the at least one chip region in at least a portion of the inner side of said first part.
12. A semiconductor device according to claim 11, wherein said fifth semiconductor layer forms a punch-through stopper layer.
13. A semiconductor device according to claim 11,
- wherein a second groove part penetrating from said first surface of said semiconductor substrate through said third semiconductor layer is formed between the first groove parts;
- wherein said fourth semiconductor layer is formed to cover at least a portion of the bottoms of said second groove parts, and
- wherein said first electrode is formed to fill up at least a portion of said second groove parts.
14. A semiconductor device including a plurality of vertical power MISFETs having trench gate electrodes over a semiconductor substrate, said plurality of vertical power MISFETs each comprising:
- a source region formed at the top surface side of said semiconductor substrate;
- a drain region formed at the back surface of said semiconductor substrate; and
- a channel forming region formed between said source region and said drain region;
- wherein a groove for forming said trench gate electrodes is about or less than 1 μm in depth; and
- wherein a punch-through stopper layer is formed inside said channel forming region.
15. A semiconductor device according to claim 14, wherein said trench gate electrodes are electrically connected to at least one gate finger portion lower in resistivity than said trench gate electrodes.
16. A semiconductor device including a plurality of vertical power MISFETs, comprising:
- a semiconductor substrate;
- grooves formed in the top surface of said semiconductor substrate extending in a first direction;
- a gate insulator formed in said respective grooves;
- a gate electrode formed over said gate insulator in the respective grooves;
- a source region formed at said top surface side of said semiconductor substrate;
- a drain region formed at said back surface side of said semiconductor substrate; and
- a channel forming region formed between said source region and the drain region;
- wherein a gate capacitance of said gate electrodes is less than or equal to 1×10−3 pF per 1 μm in said first direction, wherein a voltage of 0V is applied to said gate electrode and said source region and a voltage of less than 10V is applied to said drain region at a frequency of about 1 MHz; and
- wherein a punch-through stopper layer is formed inside said channel forming region.
17. A semiconductor device including a plurality of MISFETs formed in a chip region of a semiconductor substrate, comprising:
- a first semiconductor layer having a first conductivity type, formed over the top surface of said semiconductor substrate;
- a second semiconductor layer having a second conductivity type opposite to said first conductivity type, formed over said first semiconductor layer;
- a plurality of first groove parts less than 1 μm in depth, formed in said top surface of said semiconductor substrate, and penetrating from said top surface of said semiconductor substrate through said second semiconductor layer, at least a portion of the bottom thereof being in contact with said first semiconductor layer;
- a first insulating film formed over said sidewall and bottom of each of said first groove parts;
- a first conductor formed over said first insulating film, wherein said first conductor fills a portion of said first groove parts;
- a third semiconductor layer having said first conductivity type, formed in said second semiconductor layer adjacent to said respective first groove parts;
- a fourth semiconductor layer having said second conductivity type, formed in said second semiconductor layer between said first groove parts adjacent to each other;
- a first electrode electrically connected to said third semiconductor layer and said fourth semiconductor layer; and
- a second electrode electrically connected to said first conductor, formed of a second conductor lower in resistivity than said first conductor;
- wherein said first semiconductor layer and said third semiconductor layer form one selected form the group consisting of a source and a drain of each of said plurality of MISFETs and the second semiconductor layer forms at least one channel forming region of each of said plurality of MISFETs, and
- wherein said second electrode has a first part formed along the periphery of said chip region and a second part extended in said chip region at the inner side of said first part.
18. A semiconductor device including a plurality of MISFETs, comprising:
- a first semiconductor layer having a first conductivity type, formed over a first surface of a semiconductor substrate;
- a second semiconductor layer having a second conductivity type opposite to said first conductivity type, formed over said first semiconductor layer;
- a plurality of first groove parts less than 1 μm in depth, formed in the first surface of said semiconductor substrate, wherein at least a portion of the plurality of first groove parts are in contact with said first semiconductor layer;
- a first insulating film formed over a side and a bottom of each of said plurality of first groove parts;
- a first conductor formed over said first insulating film, wherein said first conductor fills at least one portion of the plurality of the first groove parts;
- a third semiconductor layer having said first conductivity type, formed in said second semiconductor layer adjacent to said plurality of first groove parts;
- a fourth semiconductor layer having said second conductivity type, formed in said second semiconductor layer between adjacent ones of said plurality of first groove parts; and
- a first electrode electrically connected to said third semiconductor layer and said fourth semiconductor layer,
- wherein said first semiconductor layer and said third semiconductor layer form one selected from the group consisting of a source and a drain of each of said plurality of MISFETs, said second semiconductor layer forms at least one channel forming region of each of said plurality of MISFETs, and wherein said first conductor is formed of a stacked silicon film and one selected from the group consisting of a silicon compound film and a metal film.
19-21. (Cancelled)
22. A semiconductor device, comprising:
- at least one epitaxial layer formed over a first surface of a semiconductor substrate;
- at least one transistor trench gate protruding into said epitaxial layer; and
- a punch-through stopper layer formed on said epitaxial layer and surrounding said trench gate;
- wherein said punch-through stopper layer has a substantially flat impurity profile, and a depth of about 0.1 to about 0.4 μm.
Type: Application
Filed: Jul 8, 2004
Publication Date: Feb 10, 2005
Applicant:
Inventors: Masaki Shiraishi (Hitachi), Yoshito Nakazawa (Isesaki)
Application Number: 10/886,041