Method of forming an electrical contact
In a test system, a silicon interconnect is provided that can accommodate a packaged part, such as a Land Grid Array (LGA) package. The interconnect can be made by etching a silicon substrate to form projections therefrom; forming an insulation or passivation layer through deposition or growth; depositing a seed layer over the insulation layer; depositing a metal layer over the seed layer; and etching contact members from the seed and metal layers using a single mask step. In a preferred embodiment, the metal layer is coated with another metal layer that matches the metal of the packaged part's electrical communication nodes. In one embodiment, the contact surfaces of the silicon contact are plated in gold and are planar. Included within the scope of the current invention are at least one method of testing an LGA package and at least one method of allowing electrical communication with a packaged part.
This application is a continuation of application Ser. No. 10/423,239, filed Apr. 25, 2003, now U.S. Pat. No. 6,831,472, issued Dec. 14, 2004, which is a divisional of application Ser. No. 09/387,987, filed Sep. 1, 1999, now U.S. Pat. No. 6,556,030, issued Apr. 29, 2003.
BACKGROUND OF THE INVENTION1. Technical Field
The present invention relates generally to a device and method for providing electrical communication with a packaged integrated circuit device. More specifically, the present invention concerns a silicon interconnect and a method for fabricating a silicon interconnect for a Land Grid Array package.
2. State of the Art
In testing a semiconductor die, it is often useful to establish an electrical connection between the test equipment and the circuitry of a die. Testing may be performed on an unpackaged die that has been singulated from a semiconductor wafer, on a section of dice that is still part of the wafer, or on all of the dice on a wafer. In order to test a singular die, a partial wafer, or a full wafer, it may be beneficial to house the die structure in a temporary package such as a socket. The socket is configured to attach to a board which, in turn, is coupled to the test circuitry. One way to establish electrical communication between the die's bond pads and the socket is through the use of an interconnect. The interconnect is often made of silicon or some other etchable material, which may be coated with a conductive material to aid in electrical communication. The use of etchable materials such as silicon allows for the use of semiconductor fabrication techniques to form electrical contact members from a silicon substrate. Such techniques enable formation of electrical contact members at a pitch matching that of the die's bond pads. Silicon interconnects accommodate dice in other ways as well. For example, it is noteworthy that a die's bond pads are often made of aluminum. Given the temperatures associated with certain tests, it is important that the outermost coating of the interconnect be of some material other than aluminum; otherwise, the interconnect will permanently weld to the die during testing. Thus, it is taught in the art to coat a silicon interconnect with a material that is different from the material it will temporarily contact. Moreover, aluminum oxidizes relatively easily and, as a result, a die's aluminum bond pads are often covered with a thin film of nonconductive aluminum oxide. An interconnect must penetrate this oxide to reach the conductive aluminum of the bond pad in order to establish good electrical contact. To achieve this, it is taught to include fabrication steps that provide penetrating elements, such as blades, on the top of each interconnect contact. Steps that provide such elements are addressed in more detail in U.S. Pat. Nos. 5,326,428 and 5,419,807. These elements, while considered to be an improvement over flat contacts to a die's bond pads (see, for example, U.S. Pat. No. 5,607,818), necessarily cause damage to the bond pads and may shorten their useful life. Moreover, there is a risk that the elements will break off of the interconnect's contact.
These fabrication steps result in an interconnect that is configured to be inserted into the socket, receive a die's bond pads therein, and connect them to electrical terminals of the socket. Given the material of the interconnect and its placement in the package, such an interconnect is often referred to as a “silicon insert.” The die is placed in the socket so that the die's bond pads are aligned with the interconnect's contact members; the socket is attached to the board; the board is coupled to the test circuitry; and testing commences.
After testing, the die may be removed from the socket. The interconnect may be removed as well, perhaps to be replaced by another interconnect having a different arrangement of contact members for another die. Dice that do not pass testing may be discarded, while those that do pass may undergo further processing, such as a bum-in process, and packaging.
Concerning the packaging of a die, there are varying degrees and types of packaging that a die may undergo. For example, a die may be configured as a “flip chip,” wherein conductive material such as solder balls is attached directly to the bond pads or electrical traces formed in the surface of the die; the die is then “flipped,” or mounted face down, so that the solder balls may connect with contact members of another device, such as a carrier substrate. Another example is a “chip scale package,” which includes a die along with one or more minimal package elements, such as an encapsulating material in the form of a thin protective coating formed of glass or other materials. Such a coating may be bonded at least to the active surface of the die and edges thereof and sometimes to the sides and back side of the die as well. In addition, solder balls may be attached to electrical traces in the surface of the die or directly to the die's bond pads through openings in the encapsulating material in order to provide the aforementioned “flip chip” configuration. A Ball Grid Array (BGA) package serves as yet another example that involves even more packaging: the die is wire bonded to a substrate and encapsulated, and an array of solder balls on one side of the substrate is bonded to electrical traces leading through the substrate to the die. Alternatively, the package may comprise a Land Grid Array (LGA), which is similar to a BGA, except that flat contact pads—or lands—serve as external electrical communication nodes on the substrate instead of solder balls. Similarly, if an array of pins serves as the external electrical communication nodes for the package, such a package is known as a Pin Grid Array (PGA).
Other types of packages known in the art include dual in-line packages (DIP), wherein the leads extending from the package define two lines. Zigzag in-line packages (ZIP) have a line of leads, wherein every other lead extends into one of two planes (see U.S. Pat. No. 4,790,779). Leadless chip carrier (LCC) packages use sockets or conductive pads in place of leads and are configured to directly connect to a circuit board (see U.S. Pat. No. 5,375,320). Small outline packages (SOP) and thin small outline packages (TSOP) use a plastic ring around the package to contact the far end of the leads extending straight from two opposing edges of the package. The plastic ring can be removed after testing, and the leads may then be bent as needed. Quad flat pack (QFP) packages are similar to the SOPs in that a plastic ring surrounds the package and contacts the far end of the leads. In the QFP, however, the leads extend from four sides of the package (see also
As for testing these packaged dice, current methods of doing so also have problems. For example, testing LGA packages involves contacting the lands of the LGA with pins that have been stamped from a metal sheet. Each pin is placed within a hole that is one of an array of holes found within a plastic mold. This mold keeps an array of pins aligned with the package's array of lands. Test equipment may then access the lands through these pins. Unfortunately, there are several problems with using such pins. First, as the overall size of packages becomes smaller, the area of the lands decreases, as does the space between the lands. It is difficult for the stamped pins/plastic mold formation process to match the rate at which die packages are shrinking. In addition, using such pins often results in high inductance, thereby interfering with testing. Moreover, as with the silicon interconnects and the die bond pads, there exists the risk of a scrubbing action of the pins against the lands, which could damage both the pins and the lands.
Thus, there is a need in the art for improved testing structures and methods, including a need for improved temporary packaging for testing dice that have already undergone some degree of packaging. Included within this need is the desire to establish electrical communication between an interconnect and a related packaged die. Further, there is a more general need for improved electrical communication with a die, whether such communication is with a die as part of a permanently packaged part or a temporarily packaged part, or whether such communication is for test or non-test purposes.
BRIEF SUMMARY OF THE INVENTIONAccordingly, the current invention provides an electrical connector and a method of forming it. Many exemplary embodiments of the current invention apply semiconductor fabrication techniques to an interconnect for a packaged part while reducing if not eliminating the problems attendant with prior silicon interconnects and prior interconnects for packaged parts. Such embodiments involve forming silicon interconnects having a contact surface that is complementary to the electrical contact surface of the packaged part to be tested. In some embodiments, such as those configured to contact LGA packages, the interconnect's contact surface is planar and parallel to the packaged part's contact surface. In more general embodiments, the interconnect's contacts are non-invasive or non-penetrating with respect to the electrical contacts of the packaged part. Some of these embodiments may be described as defining “male-female” configurations between the interconnect's contact surface and that of the packaged part.
An exemplary method of fabricating interconnects such as the ones described above involve defining a projection or protrusion from a substrate; providing a passivation/insulation layer over the substrate, including the projection; providing at least one seed layer over the passivation/insulation layer; providing at least one metal layer over the seed layer; and simultaneously patterning the metal layer and seed layer. In a preferred embodiment, the metal layer of the interconnect is the same metal as the packaged part's contact points.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
FIGS. 12A-E disclose an exemplary embodiment of the current invention.
FIGS. 13A-E disclose an alternative exemplary embodiment of the current invention.
A subsequent exemplary step within the scope of the current invention is illustrated in
As mentioned above and depicted in
A patterned mask layer is then provided over the metal layer 28. The metal layer 28 and seed layer 26 are etched according to the patterned mask, and the result appears in
The conductive traces 32 and connection pads 34 are more easily distinguished in
One advantage of the method embodiment depicted in
Moreover, additional metal layers may be added without adding mask steps. Assuming that it is desirable to have a gold layer contact the packaged part being tested, it may not necessarily be desirable to have gold serving as the only layer over the seed layer. For instance, given the cost of gold, it may be preferable to deposit a different metal layer over the seed layer, wherein that layer serves as the main current-carrying layer, with a thinner plate of gold deposited thereover. In one such exemplary embodiment, the main current-carrying layer can be 500 angstroms to 4 microns thick, whereas the gold layer ranges from 200 angstroms to 1 micron in thickness. Further, a different metal layer may be able to adhere to the seed layer better than gold. Accordingly, embodiments having additional metal layers are exemplified in
Yet another exemplary embodiment appears in
Another mask-saving benefit of the exemplary embodiments discussed above is that additional masks are not used to form penetrating blades on the upper surfaces of the projections 22. In addition to allowing for a simpler fabrication process, these embodiments avoid the risk of a blade breaking off from one of the projections 22 in response to contact with the land of an LGA package. Moreover, these embodiments limit the damage done to the testing and tested devices more so than the bond-pad-penetrating blades of prior art silicon interconnects and the pins of prior packaged part testing equipment.
One skilled in the art can appreciate that, although specific embodiments of this invention have been described above for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. For example, it is possible in one exemplary embodiment to retain the mask layer used to define the projections 22 seen in
Moreover, the configuration of contact members may vary from the ones described above.
Furthermore, it is not necessary that the members have planar contact surfaces. Exemplary embodiments of the current invention also include those wherein the interconnect's contact members, while non-planar, nevertheless have portions that are configured to be parallel to corresponding portions of the packaged part's contact. An exemplary method embodiment capable of achieving such a configuration is illustrated beginning with
Concerning the use of contact members, it should be noted that contact members such as the ones described above may be used in conjunction with packages other than an LGA package. For example, as shown in
Further, not only will the above-mentioned methods and devices work for silicon inserts and interconnects in general, but they have applications in other contexts as well. For example,
As an alternative to or in addition to the electrical connectors 1400 forming part of a test head, it may be desirable to include at least one electrical connector 1500 as part of a chip carrier 1506, as seen in
Yet another alternative embodiment appears in
Moreover, the methods and devices described above are not limited to testing circumstances; rather, they could also be used for interconnect devices in permanent or semipermanent packaging. Accordingly, the invention is not limited except as stated in the claims.
Claims
1. A method of processing a substrate comprising:
- masking at least portions of the substrate using a first mask patterned after a configuration of electrical communication nodes of an LGA package;
- etching a plurality of projections from the substrate;
- forming at least two metal layers over the plurality of projections;
- forming a plurality of contact members, corresponding to the plurality of projections from the at least two metal layers using solely one additional patterned mask; and
- etching an unmasked portion of the at least two metal layers.
2. The method in claim 1, wherein:
- the method further comprises forming an insulation/passivation layer over at least portions of the substrate including the plurality of projections;
- the forming of at least two metal layers over the plurality of projections comprising forming the at least two metal layers over at least portions of the insulation/passivation layer; and
- the etching an unmasked portion of the at least two metal layers further comprising etching the at least two metal layers without etching the insulation/passivation layer.
3. The method in claim 2, wherein the forming an insulation/passivation layer comprises including the first mask as at least a portion of the insulation/passivation layer.
4. A method of coating an interconnect projection on a substrate comprising:
- forming a seed layer over the interconnect projection on the substrate;
- forming a copper layer over the seed layer; and
- forming a gold layer directly over the copper layer, the gold layer including a flat top.
5. The method in claim 4, wherein the forming a copper layer comprises electroplating copper onto the seed layer.
6. The method in claim 4, wherein the forming a copper layer comprises sputtering copper onto the seed layer.
7. The method in claim 6, wherein the forming a seed layer further comprises sputtering tungsten over the interconnect projection.
8. A process method for an electrical contact for a die having an electrical communication node, the electrical communication node having a known shape formed from a known material, the method comprising:
- forming a support structure for forming a contact for the known shape of the electrical communication node of the die;
- forming a portion of the support structure to have a shape for contacting a portion of the electrical communication node of the die;
- forming an aluminum layer over a portion of the support structure formed to have a shape for contacting a portion of the electrical communication node of the die;
- forming a zinc layer; and
- forming a contact surface, the contact surface of the same material as the material of the electrical communication node of the die.
9. The method in claim 8, further comprising forming the zinc layer after forming an aluminum layer and before forming a contact surface.
10. The method in claim 9, further comprising forming a nickel layer after forming a zinc layer and before the forming a contact surface.
11. The method in claim 10, wherein forming an aluminum layer comprises sputtering aluminum over the support structure.
12. The method in claim 11, wherein forming a zinc layer comprises exposing the aluminum layer to a zincate solution.
13. The method in claim 12, wherein forming a nickel layer comprises exposing the zinc layer to a nickel solution.
14. The method in claim 13, wherein the forming a contact surface comprises providing a selection of one of a gold surface and a palladium surface.
15. The method in claim 13, wherein the forming a contact surface comprises forming a contact surface essentially matching the shape of the electrical communication node of the die.
16. The method in claim 15, wherein forming a contact surface comprises forming an essentially flat contact surface.
17. A substrate processing method comprising:
- masking at least portions of a substrate using a first mask having a pattern for forming electrical communication nodes for an LGA package;
- etching a plurality of projections from the substrate;
- forming at least two metal layers over the plurality of projections;
- forming a plurality of contact members corresponding to the plurality of projections from the at least two metal layers using a second mask; and
- etching an unmasked portion of the at least two metal layers.
18. The method in claim 17, wherein:
- the method further comprises forming an insulation/passivation layer over at least portions of the substrate including the plurality of projections;
- the forming of at least two metal layers over the plurality of projections comprising forming the at least two metal layers over at least portions of the insulation/passivation layer; and
- the etching an unmasked portion of the at least two metal layers further comprising etching the at least two metal layers without etching the insulation/passivation layer.
19. The method in claim 18, wherein the forming an insulation/passivation layer comprises including the first mask as at least a portion of the insulation/passivation layer.
Type: Application
Filed: Dec 13, 2004
Publication Date: May 5, 2005
Inventor: Salman Akram (Boise, ID)
Application Number: 11/011,420